Add version check to keep old behaviour for IVerilog 10.x

src/exec/bsc_build_vsim_iverilog

@@ -127,6 +127,24 @@ if [ -n "$BSC_OTHER_ARGUMENTS" ]; then
   exit 1
 fi
 
+# create SFT for iverilog older than v11 (only v10 supported)
+# v11 and later use the vpi files directly
+if [[ "$(iverilog -V 2>&1 | head -n 1)" =~ "v10_" ]]; then
+    CREATESFT="yes"
+else
+CREATESFT="no"
+
+if [ "$CREATESFT" = "yes" ]; then
+  # identify the VPI wrapper C files
+  BSC_VPI_CFILES=""
+  for file in $BSC_VPI_FILES; do
+    case "$file" in \
+      vpi_wrapper_* | */vpi_wrapper_* ) \
+        BSC_VPI_CFILES="$BSC_VPI_CFILES ${file%%.o}.c" ;;
+    esac
+  done
+fi
+
 # build VPI module if needed
 if [ -n "$BSC_VPI_FILES" ]; then
   if [ "$USEDPI" = "yes" ] ; then
@@ -142,6 +160,12 @@ if [ -n "$BSC_VPI_FILES" ]; then
     CXX=c++
   fi
   VPI_LINK="-m./directc_$BSC_TOPLEVEL_MODULE.so"
+  if [ "$CREATESFT" = "yes" ]; then
+    VPI_LINK="$VPI_LINK directc_$BSC_TOPLEVEL_MODULE.sft"
+    VPI_LIBPATH=""
+  else
+    VPI_LIBPATH="-L$BLUESPECDIR/VPI"
+  fi
   LDFLAGS="$LDFLAGS $BSC_LDFLAGS"
   SHARED=`$BLUESPECDIR/exec/platform.sh c++_shared_flags`
   if [ "$VERBOSE" = "yes" ]; then
@@ -151,8 +175,16 @@ if [ -n "$BSC_VPI_FILES" ]; then
       CXX_VERBOSE=""
   fi
   $CXX $CXX_VERBOSE $LDFLAGS $SHARED -o directc_$BSC_TOPLEVEL_MODULE.so -Wl,-rpath,$BLUESPECDIR/VPI -L$BLUESPECDIR/VPI $BSC_VPI_FILES -lbdpi $BSC_C_LIB_PATH $BSC_C_LIBS $BSC_CLINK_OPTS
+  if [ "$CREATESFT" = "yes" ]; then
+    if [ -n "$BSC_VPI_CFILES" ]; then
+        grep "/* sft:" $BSC_VPI_CFILES | cut -d' ' -f3-6 > directc_$BSC_TOPLEVEL_MODULE.sft
+    else
+        touch directc_$BSC_TOPLEVEL_MODULE.sft
+    fi
+  fi
 else
   VPI_LINK=""
+  VPI_LIBPATH=""
 fi
 
 # path to Verilog files
@@ -161,11 +193,11 @@ VSIM_PATH_FLAGS=$BSC_VERILOG_DIRS
 # compile Verilog files
 if [ "$VERBOSE" = "yes" ]; then
   IV_VERBOSE="-v"
-  echo "exec: iverilog -v -o $BSC_SIM_EXECUTABLE -Wall $VSIM_PATH_FLAGS $BSC_VSIM_FLAGS -DTOP=$BSC_TOPLEVEL_MODULE -L$BLUESPECDIR/VPI $BSC_VERILOG_DEFS $BSC_VERILOG_OPTS $VPI_LINK $BSC_VERILOG_FILES"
+  echo "exec: iverilog -v -o $BSC_SIM_EXECUTABLE -Wall $VSIM_PATH_FLAGS $BSC_VSIM_FLAGS -DTOP=$BSC_TOPLEVEL_MODULE $VPI_LIBPATH $BSC_VERILOG_DEFS $BSC_VERILOG_OPTS $VPI_LINK $BSC_VERILOG_FILES"
 else
   IV_VERBOSE=""
 fi
-iverilog $IV_VERBOSE -o $BSC_SIM_EXECUTABLE -Wall $VSIM_PATH_FLAGS $BSC_VSIM_FLAGS -DTOP=$BSC_TOPLEVEL_MODULE -L$BLUESPECDIR/VPI $BSC_VERILOG_DEFS $BSC_VERILOG_OPTS $VPI_LINK $BSC_VERILOG_FILES
+iverilog $IV_VERBOSE -o $BSC_SIM_EXECUTABLE -Wall $VSIM_PATH_FLAGS $BSC_VSIM_FLAGS -DTOP=$BSC_TOPLEVEL_MODULE $VPI_LIBPATH $BSC_VERILOG_DEFS $BSC_VERILOG_OPTS $VPI_LINK $BSC_VERILOG_FILES
 status=$?
 if [ "$status" != "0" ]; then
   echo "ERROR: cannot compile Verilog files" >&2