GitHub - BitsByToader/RISC_V_PIPELINE: A pipelined implementation of the base RISC-V ISA written in verilog.

BitsByToader / RISC_V_PIPELINE Public

A pipelined implementation of the base RISC-V ISA written in verilog.

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
alu.v		alu.v
alu_control.v		alu_control.v
branch_control.v		branch_control.v
code.mem		code.mem
control_module.v		control_module.v
data_memory.v		data_memory.v
execution.v		execution.v
forwarding_unit.v		forwarding_unit.v
hazard_detection_unit.v		hazard_detection_unit.v
imm_gen.v		imm_gen.v
instruction_decode.v		instruction_decode.v
instruction_fetch.v		instruction_fetch.v
instruction_memory.v		instruction_memory.v
memory.v		memory.v
program_counter.v		program_counter.v
register_file.v		register_file.v
top.v		top.v
top_tb.v		top_tb.v
write_back.v		write_back.v