GitHub - BlackOutDevelops/VerilogProject: HDL in Digital System Design

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
FinalProject.cache/wt		FinalProject.cache/wt
FinalProject.hw		FinalProject.hw
FinalProject.ip_user_files		FinalProject.ip_user_files
FinalProject.runs		FinalProject.runs
FinalProject.srcs/sim_1/new		FinalProject.srcs/sim_1/new
FinalProject.xpr		FinalProject.xpr
README		README
VERILOG.FILE_DESCRIPTIONS		VERILOG.FILE_DESCRIPTIONS
WHAT_YOU_NEED_TO_DO		WHAT_YOU_NEED_TO_DO
clkgen.v		clkgen.v
control.v		control.v
datapath.v		datapath.v
huff_dec.out		huff_dec.out
image.dat		image.dat
mystery.dat		mystery.dat
mystery.jpg		mystery.jpg
regfile.v		regfile.v
sources		sources
stimulus.v		stimulus.v
table1.dat		table1.dat
table2.dat		table2.dat
table2.v		table2.v
test1.dat		test1.dat
test1.out		test1.out
test2.dat		test2.dat
test2.out		test2.out
top.v		top.v
vivado.jou		vivado.jou
vivado.log		vivado.log
vivado_14168.backup.jou		vivado_14168.backup.jou
vivado_14168.backup.log		vivado_14168.backup.log
vivado_1760.backup.jou		vivado_1760.backup.jou
vivado_1760.backup.log		vivado_1760.backup.log
writeoutput.v		writeoutput.v

Repository files navigation

Note: *.dat files are bitstream files

image.dat JPEG bitstream data file (verilog input)
          In order to run verilog on any test file:
	   cp test.dat image.dat
	   Change the variable, NUM_BITS, as shown in stimulus.v
	   Run your favorite verilog simulator (eg: ISE)
	   Compare huff_dec.out with test.out for test.dat