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5x10-Teensy-LC-Breakout.kicad_pcb
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(page USLetter)
(title_block
(title "5x10 Teensy LC Breakout Module")
(date "20 Jan 2017")
(rev v1.4)
(company "CERN Open Hardware License v1.2.")
(comment 1 help@browndoggadgets.com)
(comment 2 http://browndoggadgets.com/)
(comment 3 "Brown Dog Gadgets")
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(gr_text Board (at 39.624 125.476) (layer F.SilkS) (tstamp 598A1C43)
(effects (font (size 2.5 2.5) (thickness 0.4)))
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(gr_text v1.4 (at 39.624 123.444) (layer B.SilkS) (tstamp 598A1802)
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(gr_text Invention (at 39.624 121.666) (layer F.SilkS)
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(gr_text "FABRICATION NOTES\n\n1. THIS IS A 2 LAYER BOARD. \n2. EXTERNAL LAYERS SHALL HAVE 1 OZ COPPER.\n3. MATERIAL: FR4 AND 0.062 INCH +/- 10% THICK.\n4. BOARDS SHALL BE ROHS COMPLIANT. \n5. MANUFACTURE IN ACCORDANCE WITH IPC-6012 CLASS 2\n6. MASK: BOTH SIDES OF THE BOARD SHALL HAVE \n SOLDER MASK (GREEN) OVER BARE COPPER. \n7. SILK: BOTH SIDES OF THE BOARD SHALL HAVE WHITE SILK. \n DO NOT PLACE SILK OVER BARE COPPER.\n8. FINISH: ENIG.\n9. MINIMUM TRACE WIDTH - 0.006 INCH.\n MINIMUM SPACE - 0.006 INCH.\n MINIMUM HOLE DIA - 0.013 INCH. \n10. MAX HOLE PLACEMENT TOLERANCE OF +/- 0.003 INCH.\n11. MAX HOLE DIAMETER TOLERANCE OF +/- 0.003 INCH AFTER PLATING." (at 77.8256 97.6884) (layer Dwgs.User)
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(gr_text CIRCUITS (at 40.45204 74.35596) (layer F.Mask) (tstamp 5887DEDA)
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