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Source code of implemention of aes in verilog of an asic project

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Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
UVM		UVM
model/python		model/python
src		src
tb		tb
.gitattributes		.gitattributes
.gitignore		.gitignore
README.md		README.md

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This is a ASIC project of implemention of AES

The AES cipher core is fork from others, the information contained at the begin of the fiel.

The testbench is tiny, only to show it is functional.

The model also from others and the way to use it is just edit the tester.py

The UVM is added, because I found the systemverilog dpi can help me build a reliable reference model, so i can implement the UVM, and check more spec about the design. Of course it is on building!

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Source code of implemention of aes in verilog of an asic project

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