CLRadeonExtender: GCNAsm: Add instructions for NAVI DL.

CLRX · Jun 22, 2019 · b3daa32 · b3daa32
1 parent a4c9fdf
commit b3daa32
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Showing 2 changed files with 10 additions and 0 deletions.
diff --git a/CLRX/utils/GPUId.h b/CLRX/utils/GPUId.h
@@ -130,6 +130,7 @@ enum : GPUArchMask
     ARCH_GCN_1_2_4 = 0x1c,
     ARCH_GCN_1_4 = 0x18,
     ARCH_GCN_1_5 = 0x60,
+    ARCH_GCN_1_5_1 = 0x40,
     ARCH_GCN_1_1_2_4_5 = 0x7e,
     ARCH_GCN_1_2_4_5 = 0x7c,
     ARCH_GCN_1_4_5 = 0x78,

diff --git a/amdasm/GCNInstructions.cpp b/amdasm/GCNInstructions.cpp
@@ -441,6 +441,7 @@ const GCNInstruction CLRX::gcnInstrsTable[] =
     { "v_writelane_b32",     GCNENC_VOP2,   GCN_SRC1_SGPR,            2,    ARCH_GCN_1_0_1  },
     { "v_writelane_b32",     GCNENC_VOP3A,  GCN_VOP3_VOP2_DS01|GCN_VOP3_SRC1_SGPR,
         258,  ARCH_GCN_1_0_1  },
+    { "v_dot2c_f32_f16",     GCNENC_VOP2,   GCN_F16LIT,               2,    ARCH_NAVI_DL  },
     { "v_add_f32",           GCNENC_VOP2,   GCN_FLOATLIT,             3,    ARCH_GCN_1_0_1_5  },
     { "v_add_f32",           GCNENC_VOP3A,  GCN_VOP3_VOP2_DS01,       259,  ARCH_GCN_1_0_1_5  },
     { "v_sub_f32",           GCNENC_VOP2,   GCN_FLOATLIT,             4,    ARCH_GCN_1_0_1_5  },
@@ -461,6 +462,7 @@ const GCNInstruction CLRX::gcnInstrsTable[] =
     { "v_mul_u32_u24",       GCNENC_VOP3A,  GCN_VOP3_VOP2_DS01,       267,  ARCH_GCN_1_0_1_5  },
     { "v_mul_hi_u32_u24",    GCNENC_VOP2,   GCN_STDMODE,              12,   ARCH_GCN_1_0_1_5  },
     { "v_mul_hi_u32_u24",    GCNENC_VOP3A,  GCN_VOP3_VOP2_DS01,       268,  ARCH_GCN_1_0_1_5  },
+    { "v_dot4c_i32_i8",      GCNENC_VOP2,   GCN_STDMODE,              13,   ARCH_NAVI_DL  },
     { "v_min_legacy_f32",    GCNENC_VOP2,   GCN_FLOATLIT,             13,   ARCH_GCN_1_0_1  },
     { "v_min_legacy_f32",    GCNENC_VOP3A,  GCN_VOP3_VOP2_DS01,       269,  ARCH_GCN_1_0_1  },
     { "v_max_legacy_f32",    GCNENC_VOP2,   GCN_FLOATLIT,             14,   ARCH_GCN_1_0_1  },
@@ -2545,6 +2547,13 @@ const GCNInstruction CLRX::gcnInstrsTable[] =
     { "v_pk_mul_f16",        GCNENC_VOP3P,  GCN_SRC2_NONE,            16, ARCH_GCN_1_5   },
     { "v_pk_min_f16",        GCNENC_VOP3P,  GCN_SRC2_NONE,            17, ARCH_GCN_1_5   },
     { "v_pk_max_f16",        GCNENC_VOP3P,  GCN_SRC2_NONE,            18, ARCH_GCN_1_5   },
+    { "v_dot2_f32_f16",      GCNENC_VOP3P,  GCN_STDMODE,              19, ARCH_NAVI_DL   },
+    { "v_dot2_i32_i16",      GCNENC_VOP3P,  GCN_STDMODE,              20, ARCH_NAVI_DL   },
+    { "v_dot2_u32_u16",      GCNENC_VOP3P,  GCN_STDMODE,              21, ARCH_NAVI_DL   },
+    { "v_dot4_i32_i8",       GCNENC_VOP3P,  GCN_STDMODE,              22, ARCH_NAVI_DL   },
+    { "v_dot4_u32_u8",       GCNENC_VOP3P,  GCN_STDMODE,              23, ARCH_NAVI_DL   },
+    { "v_dot8_i32_i4",       GCNENC_VOP3P,  GCN_STDMODE,              24, ARCH_NAVI_DL   },
+    { "v_dot8_u32_u4",       GCNENC_VOP3P,  GCN_STDMODE,              25, ARCH_NAVI_DL   },
     { "v_fma_mix_f32",       GCNENC_VOP3P,  GCN_STDMODE,              32, ARCH_GCN_1_5   },
     { "v_fma_mixlo_f16",     GCNENC_VOP3P,  GCN_STDMODE,              33, ARCH_GCN_1_5   },
     { "v_fma_mixhi_f16",     GCNENC_VOP3P,  GCN_STDMODE,              34, ARCH_GCN_1_5   },