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made another pipeline reg and fixed some syntax
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Christer
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Oct 13, 2012
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1 @@ | ||
work |
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vhdl work "reg_exmem.vhd" |
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Release 12.4 - xst M.81d (nt64) | ||
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. | ||
--> Parameter TMPDIR set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst/projnav.tmp | ||
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Total REAL time to Xst completion: 0.00 secs | ||
Total CPU time to Xst completion: 0.09 secs | ||
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--> Parameter xsthdpdir set to C:/Users/chribru/Desktop/GitHub/tdt4255/oving1/xst | ||
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Total REAL time to Xst completion: 0.00 secs | ||
Total CPU time to Xst completion: 0.09 secs | ||
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--> Reading design: reg_exmem.prj | ||
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TABLE OF CONTENTS | ||
1) Synthesis Options Summary | ||
2) HDL Parsing | ||
3) HDL Elaboration | ||
4) HDL Synthesis | ||
4.1) HDL Synthesis Report | ||
5) Advanced HDL Synthesis | ||
5.1) Advanced HDL Synthesis Report | ||
6) Low Level Synthesis | ||
7) Partition Report | ||
8) Design Summary | ||
8.1) Primitive and Black Box Usage | ||
8.2) Device utilization summary | ||
8.3) Partition Resource Summary | ||
8.4) Timing Report | ||
8.4.1) Clock Information | ||
8.4.2) Asynchronous Control Signals Information | ||
8.4.3) Timing Summary | ||
8.4.4) Timing Details | ||
8.4.5) Cross Clock Domains Report | ||
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========================================================================= | ||
* HDL Parsing * | ||
========================================================================= | ||
Parsing VHDL file "\Users\chribru\Desktop\GitHub\tdt4255\oving1\reg_exmem.vhd" into library work | ||
Parsing entity <reg_exmem>. | ||
Parsing architecture <Behavioral> of entity <reg_exmem>. | ||
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Total REAL time to Xst completion: 3.00 secs | ||
Total CPU time to Xst completion: 3.11 secs | ||
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--> | ||
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Total memory usage is 183824 kilobytes | ||
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Number of errors : 0 ( 0 filtered) | ||
Number of warnings : 0 ( 0 filtered) | ||
Number of infos : 0 ( 0 filtered) | ||
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