Probe and report page sizes supported by MIPS hardware.

This change probes the hardware to see what page sizes are supported
by writing all ones to the PageMask register and reading it back as
suggested by "MIPS Architecture For Programmers Volume III".  The
page sizes the hardware supports is reported the same time the
information about the MMU/TLB is printed.

Sponsored by:       DARPA, AFRL

sys/mips/include/cpuinfo.h

@@ -54,6 +54,7 @@ struct mips_cpuinfo {
 	u_int8_t	cpu_rev;
 	u_int8_t	cpu_impl;
 	u_int8_t	tlb_type;
+	u_int32_t	tlb_pgmask;
 	u_int16_t	tlb_nentries;
 	u_int8_t	icache_virtual;
 	boolean_t	cache_coherent_dma;

sys/mips/include/pte.h

@@ -188,4 +188,17 @@ typedef	pt_entry_t *pd_entry_t;
 #endif
 
 #endif /* LOCORE */
+
+/* PageMask Register (CP0 Register 5, Select 0) Values */
+#define	MIPS3_PGMASK_MASKX	0x00001800
+#define	MIPS3_PGMASK_4K		0x00000000
+#define	MIPS3_PGMASK_16K	0x00006000
+#define	MIPS3_PGMASK_64K	0x0001e000
+#define	MIPS3_PGMASK_256K	0x0007e000
+#define	MIPS3_PGMASK_1M		0x001fe000
+#define	MIPS3_PGMASK_4M		0x007fe000
+#define	MIPS3_PGMASK_16M	0x01ffe000
+#define	MIPS3_PGMASK_64M	0x07ffe000
+#define	MIPS3_PGMASK_256M	0x1fffe000
+
 #endif /* !_MACHINE_PTE_H_ */

sys/mips/mips/cpu.c

@@ -274,6 +274,14 @@ mips_get_identity(struct mips_cpuinfo *cpuinfo)
 	    * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways;
 	cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize 
 	    * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways;
+
+	/*
+	 * Probe PageMask register to see what sizes of pages are supported
+	 * by writing all one's and then reading it back.
+	 */
+	mips_wr_pagemask(~0);
+	cpuinfo->tlb_pgmask = mips_rd_pagemask();
+	mips_wr_pagemask(MIPS3_PGMASK_4K);
 }
 
 void
@@ -349,7 +357,30 @@ cpu_identify(void)
 		} else if (cpuinfo.tlb_type == MIPS_MMU_FIXED) {
 			printf("Fixed mapping");
 		}
-		printf(", %d entries\n", cpuinfo.tlb_nentries);
+		printf(", %d entries ", cpuinfo.tlb_nentries);
+
+		if (cpuinfo.tlb_pgmask) {
+			printf("(");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_MASKX)
+				printf("1K ");
+			printf("4K ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_16K)
+				printf("16K ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_64K)
+				printf("64K ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_256K)
+				printf("256K ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_1M)
+				printf("1M ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_16M)
+				printf("16M ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_64M)
+				printf("64M ");
+			if (cpuinfo.tlb_pgmask & MIPS3_PGMASK_256M)
+				printf("256M ");
+			printf("pg sizes)");
+		}
+		printf("\n");
 	}
 
 	printf("  L1 i-cache: ");