[CHERI-RISC-V] Expand capability AtomicRMW XCHG in hybrid mode

This allows expanding e.g. `atomicrmw xchg i32 addrspace(200)*` without a
library call. Code generation could be improved by adding an explicit
pseudo but that can be done as a follow-up change

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -9299,7 +9299,7 @@ RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
   if (DL.isFatPointer(AI->getPointerOperand()->getType())) {
     if (!RISCVABI::isCheriPureCapABI(Subtarget.getTargetABI()) &&
         AI->getOperation() == AtomicRMWInst::Xchg &&
-        DL.isFatPointer(AI->getPointerOperand()->getType()))
+        DL.isFatPointer(AI->getValOperand()->getType()))
       return AtomicExpansionKind::CmpXChg;
     return AtomicExpansionKind::None;
   }