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University of Moratuwa, Sri Lanka
- http://chandula-nethmal.blogspot.com/
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Implemet-a-UART-link-on-FPGA-with-verilog
Implemet-a-UART-link-on-FPGA-with-verilog PublicImplement a UART(Universal Asynchronous Receiver Transmitter) link on an Altera (now Intel) DE2 115 development board with cyclone IV FPGA using verilog HDL.
Verilog 3
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Processor-Design-and-Implementation-on-a-FPGA
Processor-Design-and-Implementation-on-a-FPGA PublicOverview The objective of this project is to design object specified microprocessor and a Central Processing Unit in order to downscale an image. As steps of above task, we have to simulate it usin…
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UART-communication-Link-on-a-FPGA-using-Verilog-HDL
UART-communication-Link-on-a-FPGA-using-Verilog-HDL PublicThis post is regarding a HDL implementation of a UART(Universal Asynchronous Receiver Transmitter) for one of our university fourth semester projects.For the project we were supposed to implement a…
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Accident-Alerting-System-Using-GSM-shield
Accident-Alerting-System-Using-GSM-shield PublicThis was a kind of basic project I have involved with one of my friend who was studying at a engineering education Institute. The target was an accident alerting system for a vehicle. When the car …
C++ 1
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