[COREV] Define ALU instructions (openhwgroup#10)

Signed-off-by: Serkan Muhcu <serkan.muhcu@student.uni-tuebingen.de>
CharKeaney · Aug 18, 2022 · bb0475c · bb0475c
1 parent bab2fa8
commit bb0475c
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diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1205,6 +1205,9 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1);
   case Match_InvalidUImm12:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 12) - 1);
+  case Match_InvalidSImm5:
+    return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4),
+                                      (1 << 4) - 1);
   case Match_InvalidSImm6:
     return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 5),
                                       (1 << 5) - 1);

diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
@@ -454,11 +454,19 @@ def HasExtXCoreVMac
     : Predicate<"Subtarget->hasExtXCoreVMac()">,
                AssemblerPredicate<(any_of FeatureExtXCoreVMac),
                "'Xcorevmac' (Multiply-Accumulate)">;
+// CORE-V ALU Extension
+def FeatureExtXCoreVAlu
+    : SubtargetFeature<"xcorevalu", "HasExtXCoreVAlu", "true",
+                       "'Xcorevalu' (ALU Operations)">;
+def HasExtXCoreVAlu
+    : Predicate<"Subtarget->hasExtXCoreVAlu()">,
+               AssemblerPredicate<(any_of FeatureExtXCoreVAlu),
+               "'Xcorevalu' (ALU Operations)">;
 // All CORE-V extensions
 def FeatureExtXCoreV
     : SubtargetFeature<"xcorev", "HasExtXCoreV", "true",
                        "'Xcorev' (CORE-V extensions)",
-                       [FeatureExtXCoreVHwlp, FeatureExtXCoreVMac]>;
+                       [FeatureExtXCoreVHwlp, FeatureExtXCoreVMac, FeatureExtXCoreVAlu]>;
 def HasExtXCoreV : Predicate<"Subtarget->hasExtXCoreV()">,
                               AssemblerPredicate<(all_of FeatureExtXCoreV),
                               "'Xcorev' (CORE-V extensions)">;

diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsCOREV.td
@@ -113,3 +113,82 @@ class RVInstMac16I<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
   let Inst{11-7} = rd;
   let Opcode = OPC_CUSTOM2.Value;
 }
+
+class RVInstAlu_rri<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
+                    string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
+  bits<5> imm5;
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-30} = funct2;
+  let Inst{29-25} = imm5;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_CUSTOM2.Value;
+}
+
+class RVInstAlu_rr<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
+                   string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = rs2;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP.Value;
+}
+
+class RVInstAlu_ri<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
+                   string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
+  bits<5> imm5;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = imm5;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP.Value;
+}
+
+class RVInstAlu_r<bits<7> funct7, bits<3> funct3, dag outs, dag ins,
+                  string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatOther> {
+  bits<5> rs2;
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{31-25} = funct7;
+  let Inst{24-20} = 0b00000;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-7} = rd;
+  let Opcode = OPC_OP.Value;
+}
+
+class RVInstImmBranch<bits<3> funct3, dag outs, dag ins,
+                      string opcodestr, string argstr, list<dag> pattern>
+    : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatB> {
+  bits<12> imm12;
+  bits<5> imm5;
+  bits<5> rs1;
+
+  let Inst{31} = imm12{11};
+  let Inst{30-25} = imm12{9-4};
+  let Inst{24-20} = imm5;
+  let Inst{19-15} = rs1;
+  let Inst{14-12} = funct3;
+  let Inst{11-8} = imm12{3-0};
+  let Inst{7} = imm12{10};
+  let Opcode = OPC_BRANCH.Value;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoCOREV.td
@@ -67,6 +67,7 @@ def cv_uimm12 : Operand<XLenVT>,
   let OperandNamespace = "RISCVOp";
 }
 
+
 //===----------------------------------------------------------------------===//
 // CORE-V specific instructions
 //===----------------------------------------------------------------------===//
@@ -176,6 +177,121 @@ let Predicates = [HasExtXCoreVMac], hasSideEffects = 0, mayLoad = 0, mayStore =
                     Sched<[]>;
 } // Predicates = [HasExtXCoreVMac], hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
+let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+  // General ALU Operations
+  def CV_ABS    : RVInstAlu_r<0b0000010, 0b000, (outs GPR:$rd), (ins GPR:$rs1),
+                              "cv.abs", "$rd, $rs1", []>,
+                  Sched<[]>;
+  def CV_SLET   : RVInstAlu_rr<0b0000010, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.slet", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_SLETU  : RVInstAlu_rr<0b0000010, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.sletu", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_MIN    : RVInstAlu_rr<0b0000010, 0b100, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.min", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_MINU   : RVInstAlu_rr<0b0000010, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.minu", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_MAX    : RVInstAlu_rr<0b0000010, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.max", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_MAXU   : RVInstAlu_rr<0b0000010, 0b111, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.maxu", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_EXTHS  : RVInstAlu_r<0b0001000, 0b100, (outs GPR:$rd), (ins GPR:$rs1),
+                              "cv.exths", "$rd, $rs1", []>,
+                  Sched<[]>;
+  def CV_EXTHZ  : RVInstAlu_r<0b0001000, 0b101, (outs GPR:$rd), (ins GPR:$rs1),
+                              "cv.exthz", "$rd, $rs1", []>,
+                  Sched<[]>;
+  def CV_EXTBS  : RVInstAlu_r<0b0001000, 0b110, (outs GPR:$rd), (ins GPR:$rs1),
+                              "cv.extbs", "$rd, $rs1", []>,
+                  Sched<[]>;
+  def CV_EXTBZ  : RVInstAlu_r<0b0001000, 0b111, (outs GPR:$rd), (ins GPR:$rs1),
+                              "cv.extbz", "$rd, $rs1", []>,
+                  Sched<[]>;
+
+  def CV_CLIP   : RVInstAlu_ri<0b0001010, 0b001, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
+                               "cv.clip", "$rd, $rs1, $imm5", []>,
+                  Sched<[]>;
+  def CV_CLIPU  : RVInstAlu_ri<0b0001010, 0b010, (outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5),
+                               "cv.clipu", "$rd, $rs1, $imm5", []>,
+                  Sched<[]>;
+  def CV_CLIPR  : RVInstAlu_rr<0b0001010, 0b101, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.clipr", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+  def CV_CLIPUR : RVInstAlu_rr<0b0001010, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.clipur", "$rd, $rs1, $rs2", []>,
+                  Sched<[]>;
+
+  def CV_ADDN   : RVInstAlu_rri<0b00, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addn", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_ADDUN  : RVInstAlu_rri<0b10, 0b010, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addun", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_ADDRN  : RVInstAlu_rri<0b00, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addrn", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_ADDURN : RVInstAlu_rri<0b10, 0b110, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.addurn", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_SUBN   : RVInstAlu_rri<0b00, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.subn", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_SUBUN  : RVInstAlu_rri<0b10, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.subun", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_SUBRN  : RVInstAlu_rri<0b00, 0b111, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.subrn", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+  def CV_SUBURN : RVInstAlu_rri<0b10, 0b111, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+                                "cv.suburn", "$rd, $rs1, $rs2, $imm5", []>,
+                  Sched<[]>;
+} // Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM2.Value, Constraints = "$rd = $rd_wb" in {
+  def CV_ADDNR   : RVInstAlu_rr<0b0100000, 0b010, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addnr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_ADDUNR  : RVInstAlu_rr<0b1100000, 0b010, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addunr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_ADDRNR  : RVInstAlu_rr<0b0100000, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addrnr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_ADDURNR : RVInstAlu_rr<0b1100000, 0b110, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.addurnr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_SUBNR   : RVInstAlu_rr<0b0100000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.subnr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_SUBUNR  : RVInstAlu_rr<0b1100000, 0b011, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.subunr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_SUBRNR  : RVInstAlu_rr<0b0100000, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.subrnr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+  def CV_SUBURNR : RVInstAlu_rr<0b1100000, 0b111, (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
+                                "cv.suburnr", "$rd, $rs1, $rs2", []>,
+                   Sched<[]>;
+
+} // Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Opcode = OPC_CUSTOM2.Value, Constraints = "$rd = $rd_wb"
+
+let Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, isBranch = 1, isTerminator = 1 in {
+  // Immediate branching operations
+  def CV_BEQIMM : RVInstImmBranch<0b010, (outs), (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+                                  "cv.beqimm", "$rs1, $imm5, $imm12", []>,
+                  Sched<[]>;
+  def CV_BNEIMM : RVInstImmBranch<0b011, (outs), (ins GPR:$rs1, simm5:$imm5, simm13_lsb0:$imm12),
+                                  "cv.bneimm", "$rs1, $imm5, $imm12", []>,
+                  Sched<[]>;
+
+} // Predicates = [HasExtXCoreVAlu], hasSideEffects = 0, mayLoad = 0, mayStore = 0, isBranch = 1, isTerminator = 1
+
+
 //===----------------------------------------------------------------------===//
 // CORE-V specific helper fragments
 //===----------------------------------------------------------------------===//
@@ -232,45 +348,45 @@ def : Pat<(muls GPR:$rs1, GPR:$rs2),
           (CV_MULS GPR:$rs1, GPR:$rs2)>;
 def : Pat<(mulhhs GPR:$rs1, GPR:$rs2),
           (CV_MULHHS GPR:$rs1, GPR:$rs2)>;
-def : Pat<(sra (muls GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULSN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(sra (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULHHSN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(shiftRound (muls GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULSRN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(shiftRound (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULHHSRN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
+def : Pat<(sra (muls GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULSN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(sra (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULHHSN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(shiftRound (muls GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULSRN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(shiftRound (mulhhs GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULHHSRN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
 def : Pat<(mulu GPR:$rs1, GPR:$rs2),
           (CV_MULU GPR:$rs1, GPR:$rs2)>;
 def : Pat<(mulhhu GPR:$rs1, GPR:$rs2),
           (CV_MULHHU GPR:$rs1, GPR:$rs2)>;
-def : Pat<(srl (mulu GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULUN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(srl (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULHHUN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(ushiftRound (mulu GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULURN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(ushiftRound (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MULHHURN GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-
-def : Pat<(sra (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(sra (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACHHSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(shiftRound (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(shiftRound (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACHHSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-
-def : Pat<(srl (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(srl (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACHHUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(ushiftRound (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
-def : Pat<(ushiftRound (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$Is3),
-          (CV_MACHHURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$Is3)>;
+def : Pat<(srl (mulu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULUN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(srl (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULHHUN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(ushiftRound (mulu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULURN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(ushiftRound (mulhhu GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MULHHURN GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+
+def : Pat<(sra (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(sra (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACHHSN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(shiftRound (macs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(shiftRound (machhs GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACHHSRN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+
+def : Pat<(srl (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(srl (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACHHUN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(ushiftRound (macu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
+def : Pat<(ushiftRound (machhu GPR:$rd, GPR:$rs1, GPR:$rs2), uimm5:$imm5),
+          (CV_MACHHURN GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5)>;
 
 
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -93,6 +93,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool HasExtXCoreV = false;
   bool HasExtXCoreVHwlp = false;
   bool HasExtXCoreVMac = false;
+  bool HasExtXCoreVAlu = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
@@ -193,6 +194,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   bool hasExtXCoreV() const { return HasExtXCoreV; }
   bool hasExtXCoreVHwlp() const { return HasExtXCoreVHwlp; }
   bool hasExtXCoreVMac() const { return HasExtXCoreVMac; }
+  bool hasExtXCoreVAlu() const { return HasExtXCoreVAlu; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }

diff --git a/llvm/test/MC/RISCV/corev/alu/abs-invalid.s b/llvm/test/MC/RISCV/corev/alu/abs-invalid.s
@@ -0,0 +1,14 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.abs t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.abs t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/corev/alu/abs.s b/llvm/test/MC/RISCV/corev/alu/abs.s
@@ -0,0 +1,10 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcorevalu -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+
+cv.abs t0, t1
+# CHECK-INSTR: cv.abs t0, t1
+# CHECK-ENCODING: [0xb3,0x02,0x03,0x04]
+
+cv.abs a0, a1
+# CHECK-INSTR: cv.abs a0, a1
+# CHECK-ENCODING: [0x33,0x85,0x05,0x04]
diff --git a/llvm/test/MC/RISCV/corev/alu/addn-invalid.s b/llvm/test/MC/RISCV/corev/alu/addn-invalid.s
@@ -0,0 +1,26 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcorevalu %s 2>&1 \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.addn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction