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FDCAN support for STM32H7 #38
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Original file line number | Diff line number | Diff line change |
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@@ -134,7 +134,7 @@ static bool fdcan_clock_stop(CANDriver *canp) { | |
canp->fdcan->CCCR |= FDCAN_CCCR_CSR; | ||
start = osalOsGetSystemTimeX(); | ||
end = osalTimeAddX(start, TIME_MS2I(TIMEOUT_INIT_MS)); | ||
while ((canp->fdcan->CCCR & FDCAN_CCCR_CSA) != 0U) { | ||
while ((canp->fdcan->CCCR & FDCAN_CCCR_CSA) == 0U) { | ||
if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) { | ||
return true; | ||
} | ||
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@@ -276,15 +276,22 @@ bool can_lld_start(CANDriver *canp) { | |
} | ||
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/* Configuration can be performed now.*/ | ||
canp->fdcan->CCCR = FDCAN_CCCR_CCE; | ||
canp->fdcan->CCCR |= FDCAN_CCCR_CCE; | ||
canp->fdcan->CCCR &= ~(FDCAN_CCCR_CSR | FDCAN_CCCR_CSA); | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. another bug - this meant that any bits passed in to the TEST or CCCR registers didn't get applied because this line was previously clearing the INIT flag that allows writing those registers. |
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/* Setting up operation mode except driver-controlled bits.*/ | ||
canp->fdcan->NBTP = canp->config->NBTP; | ||
canp->fdcan->DBTP = canp->config->DBTP; | ||
canp->fdcan->CCCR |= canp->config->CCCR & ~(FDCAN_CCCR_CSR | FDCAN_CCCR_CSA | | ||
FDCAN_CCCR_CCE | FDCAN_CCCR_INIT); | ||
canp->fdcan->TEST = canp->config->TEST; | ||
#ifdef STM32G4XX | ||
canp->fdcan->RXGFC = canp->config->RXGFC; | ||
#elif defined(STM32H7XX) | ||
canp->fdcan->GFC = canp->config->RXGFC; | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. this register changed name for no apparent reason? There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. I'm also not sure if this is the ChibiOS standard way to do something like this - might make more sense to put it in the registry instead. |
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#else | ||
#error "Unsupported STM32 for FDCAN LLD driver" | ||
#endif | ||
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/* Enabling interrupts, only using interrupt zero.*/ | ||
canp->fdcan->IR = (uint32_t)-1; | ||
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@@ -294,6 +301,22 @@ bool can_lld_start(CANDriver *canp) { | |
canp->fdcan->TXBTIE = FDCAN_TXBTIE_TIE; | ||
canp->fdcan->ILE = FDCAN_ILE_EINT0; | ||
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#ifdef STM32H7XX | ||
/* H7 version of FDCAN has configurable memory layout, so configure it */ | ||
canp->fdcan->SIDFC = STM32_FDCAN_FLS_NBR << 16 | SRAMCAN_FLSSA; | ||
canp->fdcan->XIDFC = STM32_FDCAN_FLE_NBR << 16 | SRAMCAN_FLESA; | ||
canp->fdcan->RXF0C = STM32_FDCAN_RF0_NBR << 16 | SRAMCAN_RF0SA; | ||
canp->fdcan->RXF1C = STM32_FDCAN_RF1_NBR << 16 | SRAMCAN_RF1SA; | ||
canp->fdcan->RXBC = SRAMCAN_RBSA; | ||
canp->fdcan->TXEFC = STM32_FDCAN_TEF_NBR << 16 | SRAMCAN_TEFSA; | ||
/* NB: this doesn't set NDTB, but sets TFQS to run in queue mode with no dedicated buffers */ | ||
canp->fdcan->TXBC = STM32_FDCAN_TB_NBR << 24 | SRAMCAN_TBSA; | ||
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/* set to use the full 18-byte size buffer elements */ | ||
canp->fdcan->TXESC = 0x007; | ||
canp->fdcan->RXESC = 0x777; | ||
#endif /* STM32H7XX */ | ||
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/* Going in active mode.*/ | ||
if (fdcan_active_mode(canp)) { | ||
osalDbgAssert(false, "CAN initialization failed, check clocks and pin config"); | ||
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This was a bug - the datasheet states that the CSA bit will be set when the device is ready for clock stop. Thus, we should spin while it's zero.