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Counter miss-documentation #41

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jbox144 opened this issue Mar 22, 2019 · 1 comment · May be fixed by #184
Open

Counter miss-documentation #41

jbox144 opened this issue Mar 22, 2019 · 1 comment · May be fixed by #184
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@jbox144
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jbox144 commented Mar 22, 2019

The counter components "zero" output is activated when the counter overflows, and the clock cycle that overflowed the counter is still high. That is why when the max value is set to 0, it will always be high. The documentation does not cover this.

@jbox144 jbox144 changed the title Counter mis-documentation Counter miss-documentation Mar 22, 2019
@Kedar-K
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Kedar-K commented Mar 22, 2019

I am on it.

Kedar-K added a commit to Kedar-K/CircuitVerseDocs that referenced this issue Mar 22, 2019
Kedar-K added a commit to Kedar-K/CircuitVerseDocs that referenced this issue Mar 22, 2019
CodeSarthak added a commit to CodeSarthak/CircuitVerseDocs that referenced this issue Dec 2, 2019
@CodeSarthak CodeSarthak linked a pull request Dec 3, 2019 that will close this issue
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