support for 11h and 12h generation of IntelCPU

Signed-off-by: SergeySlice <sergey.slice@gmail.com>
CloverHackyColor · Nov 17, 2021 · c10a0b7 · c10a0b7
1 parent 13fadd7
commit c10a0b7
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Showing 4 changed files with 28 additions and 8 deletions.
diff --git a/Include/IndustryStandard/ProcessorInfo.h b/Include/IndustryStandard/ProcessorInfo.h
@@ -194,6 +194,13 @@ enum {
 //#define CPU_MODEL_COMETLAKE_S    0xA5 /* desktop CometLake */
 #define CPU_MODEL_COMETLAKE_Y    0xA5 /* aka 10th generation Amber Lake Y */
 #define CPU_MODEL_COMETLAKE_U    0xA6
+//From Clover collection
+#define CPU_MODEL_ATOM_TM       0x86  /* Tremont */
+#define CPU_MODEL_TIGERLAKE_C   0x8C  /* 11h generation Tiger Lake */
+#define CPU_MODEL_TIGERLAKE_D   0x8D  /* 11h generation Tiger Lake */
+#define CPU_MODEL_ALDERLAKE     0x97  /* 12h generation Alder Lake */
+#define CPU_MODEL_ROCKETLAKE    0xA7  /* 11h Rocket Lake */
+
 
 #define CPU_SOCKET_UNKNOWN  0x02
 #define CPU_SOCKET_PGA478   0x0F

diff --git a/rEFIt_UEFI/Platform/StateGenerator.cpp b/rEFIt_UEFI/Platform/StateGenerator.cpp
@@ -163,10 +163,10 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
 
             cpu_noninteger_bus_ratio = ((AsmReadMsr64(MSR_IA32_PERF_STATUS) & (1ULL << 46)) != 0)?1:0;
             initial.Control.Control = (UINT16)AsmReadMsr64(MSR_IA32_PERF_STATUS);
-			  DBG("Initial control=0x%hX\n", initial.Control.Control);
+            DBG("Initial control=0x%hX\n", initial.Control.Control);
 
             maximum.Control.Control = (RShiftU64(AsmReadMsr64(MSR_IA32_PERF_STATUS), 32) & 0x1F3F) | (0x4000 * cpu_noninteger_bus_ratio);
-			  DBG("Maximum control=0x%hX\n", maximum.Control.Control);
+            DBG("Maximum control=0x%hX\n", maximum.Control.Control);
             if (GlobalConfig.Turbo) {
               maximum.Control.VID_FID.FID++;
               MsgLog("Turbo FID=0x%hhX\n", maximum.Control.VID_FID.FID);
@@ -273,8 +273,10 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
           case CPU_MODEL_COMETLAKE_S:
           case CPU_MODEL_COMETLAKE_Y:
           case CPU_MODEL_COMETLAKE_U:
-        case CPU_MODEL_TIGERLAKE_C:
-        case CPU_MODEL_TIGERLAKE_D:
+          case CPU_MODEL_TIGERLAKE_C:
+          case CPU_MODEL_TIGERLAKE_D:
+          case CPU_MODEL_ALDERLAKE:
+          case CPU_MODEL_ROCKETLAKE:
          {
             maximum.Control.Control = RShiftU64(AsmReadMsr64(MSR_PLATFORM_INFO), 8) & 0xff;
             if (gSettings.ACPI.SSDT.MaxMultiplier) {
@@ -343,6 +345,8 @@ SSDT_TABLE *generate_pss_ssdt(UINTN Number)
                     (gCPUStructure.Model == CPU_MODEL_ICELAKE) ||
                     (gCPUStructure.Model == CPU_MODEL_TIGERLAKE_C) ||
                     (gCPUStructure.Model == CPU_MODEL_TIGERLAKE_D) ||
+                    (gCPUStructure.Model == CPU_MODEL_ROCKETLAKE) ||
+                    (gCPUStructure.Model == CPU_MODEL_ALDERLAKE) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_S) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_Y) ||
                     (gCPUStructure.Model == CPU_MODEL_COMETLAKE_U)) {

diff --git a/rEFIt_UEFI/Platform/cpu.cpp b/rEFIt_UEFI/Platform/cpu.cpp
@@ -329,6 +329,8 @@ void GetCPUProperties (void)
       case CPU_MODEL_COMETLAKE_U:
       case CPU_MODEL_TIGERLAKE_C:
       case CPU_MODEL_TIGERLAKE_D:
+      case CPU_MODEL_ALDERLAKE:
+      case CPU_MODEL_ROCKETLAKE:
         msr = AsmReadMsr64(MSR_CORE_THREAD_COUNT);  //0x35
         DBG("MSR 0x35    %16llX\n", msr);
         gCPUStructure.Cores   = (UINT8)bitfield((UINT32)msr, 31, 16);
@@ -520,8 +522,11 @@ void GetCPUProperties (void)
            case CPU_MODEL_COMETLAKE_S:
            case CPU_MODEL_COMETLAKE_Y:
            case CPU_MODEL_COMETLAKE_U:
-         case CPU_MODEL_TIGERLAKE_C:
-         case CPU_MODEL_TIGERLAKE_D:
+           case CPU_MODEL_TIGERLAKE_C:
+           case CPU_MODEL_TIGERLAKE_D:
+           case CPU_MODEL_ALDERLAKE:
+           case CPU_MODEL_ROCKETLAKE:
+
             gCPUStructure.TSCFrequency = MultU64x32(gCPUStructure.CurrentSpeed, Mega); //MHz -> Hz
              gCPUStructure.CPUFrequency = gCPUStructure.TSCFrequency;
 
@@ -1400,8 +1405,10 @@ UINT16 GetAdvancedCpuType()
           case CPU_MODEL_COMETLAKE_S:
           case CPU_MODEL_COMETLAKE_Y:
           case CPU_MODEL_COMETLAKE_U:
-        case CPU_MODEL_TIGERLAKE_C:
-        case CPU_MODEL_TIGERLAKE_D:
+          case CPU_MODEL_TIGERLAKE_C:
+          case CPU_MODEL_TIGERLAKE_D:
+          case CPU_MODEL_ALDERLAKE:
+          case CPU_MODEL_ROCKETLAKE:
             if ( gCPUStructure.BrandString.contains("Core(TM) i3") )
               return 0x905; // Core i3 - Apple doesn't use it
             if ( gCPUStructure.BrandString.contains("Core(TM) i5") )

diff --git a/rEFIt_UEFI/Platform/cpu.h b/rEFIt_UEFI/Platform/cpu.h
@@ -71,11 +71,13 @@
 #define CPU_MODEL_TIGERLAKE_C   0x8C  /* 11h generation Tiger Lake */
 #define CPU_MODEL_TIGERLAKE_D   0x8D  /* 11h generation Tiger Lake */
 #define CPU_MODEL_KABYLAKE1     0x8E  /* 7h Kabylake Mobile */
+#define CPU_MODEL_ALDERLAKE     0x97  /* 12h generation Alder Lake */
 #define CPU_MODEL_KABYLAKE2     0x9E  /* 7h CoffeeLake */
 #undef CPU_MODEL_COMETLAKE_S // Jief : mistake in ProcessorInfo.h ?
 #define CPU_MODEL_COMETLAKE_S   0x9F  /* desktop Comet Lake */
 #define CPU_MODEL_COMETLAKE_Y   0xA5  /* 10h Comet Lake */
 #define CPU_MODEL_COMETLAKE_U   0xA6  /* 10h Comet Lake */
+#define CPU_MODEL_ROCKETLAKE    0xA7  /* 11h Rocket Lake */
 
 #define CPU_VENDOR_INTEL        0x756E6547
 #define CPU_VENDOR_AMD          0x68747541