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vout: support vout2 command for viu2 display [1/1]
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PD#TV-5428

Problem:
need viu2 display support

Solution:
add vout2 management
you can use "vout2 output ${outputmode}" to enable vout2 display

Verify:
x301

Change-Id: Id47e430453ebdf7c32f41d271d6e926fd5cf0f6b
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
Signed-off-by: Dongjin Kim <tobetter@gmail.com>
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@tobetter
Evoke Zhang authored and tobetter committed Feb 10, 2020
1 parent 6a4d404 commit 01a3f72
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Showing 35 changed files with 537 additions and 319 deletions.
15 changes: 0 additions & 15 deletions arch/arm/cpu/armv8/axg/hdmitx20/enc_clk_config.c
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Original file line number Diff line number Diff line change
Expand Up @@ -65,20 +65,6 @@
printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
} while(0);

// viu_channel_sel: 1 or 2
// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
{
if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
return -1;
if (viu_channel_sel == 1)
hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
else
//viu_channel_sel ==2
hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
return 0;
}

static void set_hdmitx_sys_clk(void)
{
hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
Expand Down Expand Up @@ -345,7 +331,6 @@ void set_hdmitx_clk(enum hdmi_vic vic)
return;
}
next:
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out);
set_hpll_od1(p_enc[j].od1);
Expand Down
11 changes: 9 additions & 2 deletions arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_set.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/register.h>
#include <amlogic/vout.h>
#include <amlogic/hdmi.h>
#include "hdmitx_reg.h"
#include "hdmitx_tvenc.h"
Expand Down Expand Up @@ -406,7 +407,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)

int hdmi_outputmode_check(char *mode)
{
int i, ret = -1;
int i, ret = 0xff;

for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
if (!strcmp(mode, gxbb_modes[i].sname)) {
Expand All @@ -415,8 +416,14 @@ int hdmi_outputmode_check(char *mode)
}
}

if (ret)
if (ret) {
printf("hdmitx: outputmode[%s] is invalid\n", mode);
return ret;
}
if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
ret = VIU_MUX_ENCI;
else
ret = VIU_MUX_ENCP;
return ret;
}

Expand Down
17 changes: 0 additions & 17 deletions arch/arm/cpu/armv8/axg/hdmitx20/hdmitx_tvenc.c
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Original file line number Diff line number Diff line change
Expand Up @@ -52,7 +52,6 @@ static const struct reg_t tvregs_720p[] = {
{P_ENCP_VIDEO_VSO_BLINE, 0},
{P_ENCP_VIDEO_VSO_ELINE, 5},
{P_ENCP_VIDEO_MAX_LNCNT, 749},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -88,7 +87,6 @@ static const struct reg_t tvregs_720p_50hz[] = {
{P_ENCP_VIDEO_MODE_ADV, 0x0019},
{P_ENCP_VIDEO_SYNC_MODE, 0x407},
{P_ENCP_VIDEO_YC_DLY, 0},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -120,7 +118,6 @@ static const struct reg_t tvregs_480i[] = {
{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
{P_ENCP_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -157,7 +154,6 @@ static const struct reg_t tvregs_480p[] = {
{P_ENCP_VIDEO_VSO_BLINE, 0},
{P_ENCP_VIDEO_SY_VAL, 8},
{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -194,7 +190,6 @@ static const struct reg_t tvregs_576i[] = {
{P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
{P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
{P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
{P_VPU_VIU_VENC_MUX_CTRL, 0x5},
{P_ENCP_VIDEO_EN, 0},
{P_ENCI_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -231,7 +226,6 @@ static const struct reg_t tvregs_576p[] = {
{P_ENCP_VIDEO_VSO_BLINE, 0},
{P_ENCP_VIDEO_SY_VAL, 8},
{P_ENCP_VIDEO_SY2_VAL, 0x1d8},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -271,7 +265,6 @@ static const struct reg_t tvregs_1080i[] = {
{P_ENCP_VIDEO_MODE, 0x5ffc},
{P_ENCP_VIDEO_MODE_ADV, 0x0019},
{P_ENCP_VIDEO_SYNC_MODE, 0x207},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -307,7 +300,6 @@ static const struct reg_t tvregs_1080i_50hz[] = {
{P_ENCP_VIDEO_MODE, 0x5ffc},
{P_ENCP_VIDEO_MODE_ADV, 0x0019},
{P_ENCP_VIDEO_SYNC_MODE, 0x7},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -341,7 +333,6 @@ static const struct reg_t tvregs_1080p[] = {
{P_ENCP_VIDEO_VSO_BLINE, 0},
{P_ENCP_VIDEO_VSO_ELINE, 5},
{P_ENCP_VIDEO_MAX_LNCNT, 1124},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_VENC_VIDEO_PROG_MODE, 0x100},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
Expand Down Expand Up @@ -381,7 +372,6 @@ static const struct reg_t tvregs_1080p_50hz[] = {
{P_ENCP_VIDEO_SYNC_MODE, 0x7},
{P_ENCP_VIDEO_YC_DLY, 0},
{P_ENCP_VIDEO_RGB_CTRL, 2},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -421,7 +411,6 @@ static const struct reg_t tvregs_1080p_24hz[] = {
{P_ENCP_VIDEO_SYNC_MODE, 0x7},
{P_ENCP_VIDEO_YC_DLY, 0},
{P_ENCP_VIDEO_RGB_CTRL, 2},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCI_VIDEO_EN, 0},
{P_ENCP_VIDEO_EN, 1},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -454,7 +443,6 @@ static const struct reg_t tvregs_4k2k_30hz[] = {
{P_ENCP_VIDEO_VSO_ELINE, 53},
{P_ENCP_VIDEO_MAX_LNCNT, 2249},
{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -487,7 +475,6 @@ static const struct reg_t tvregs_4k2k_25hz[] = {
{P_ENCP_VIDEO_VSO_ELINE, 53},
{P_ENCP_VIDEO_MAX_LNCNT, 2249},
{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -520,7 +507,6 @@ static const struct reg_t tvregs_4k2k_24hz[] = {
{P_ENCP_VIDEO_VSO_ELINE, 53},
{P_ENCP_VIDEO_MAX_LNCNT, 2249},
{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand Down Expand Up @@ -553,7 +539,6 @@ static const struct reg_t tvregs_4k2k_smpte[] = {
{P_ENCP_VIDEO_VSO_ELINE, 53},
{P_ENCP_VIDEO_MAX_LNCNT, 2249},
{P_ENCP_VIDEO_FILT_CTRL, 0x1000},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand All @@ -576,7 +561,6 @@ static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand All @@ -599,7 +583,6 @@ static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
{P_ENCP_VIDEO_VSO_END, 0x32,},
{P_ENCP_VIDEO_VSO_BLINE, 0x0,},
{P_ENCP_VIDEO_VSO_ELINE, 0xA,},
{P_VPU_VIU_VENC_MUX_CTRL, 0xA},
{P_ENCP_VIDEO_EN, 1},
{P_ENCI_VIDEO_EN, 0},
{MREG_END_MARKER, 0},
Expand Down
14 changes: 0 additions & 14 deletions arch/arm/cpu/armv8/g12a/hdmitx20/enc_clk_config.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -70,19 +70,6 @@
printk("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
} while (0)

// viu_channel_sel: 1 or 2
// viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.
int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
{
if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
return -1;
if (viu_channel_sel == 1)
hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
else
//viu_channel_sel ==2
hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
return 0;
}

static void set_hdmitx_sys_clk(void)
{
Expand Down Expand Up @@ -1124,7 +1111,6 @@ void hdmitx_set_clk_(struct hdmitx_dev *hdev)
}

next:
set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
set_hdmitx_sys_clk();
set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev);
if (!getenv("sspll_dis"))
Expand Down
11 changes: 9 additions & 2 deletions arch/arm/cpu/armv8/g12a/hdmitx20/hdmitx_set.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,6 +22,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/register.h>
#include <amlogic/vout.h>
#include <amlogic/hdmi.h>
#include "hdmitx_reg.h"
#include "hdmitx_tvenc.h"
Expand Down Expand Up @@ -502,7 +503,7 @@ void hdmi_tx_set(struct hdmitx_dev *hdev)

int hdmi_outputmode_check(char *mode)
{
int i, ret = -1;
int i, ret = 0xff;

for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
if (!strcmp(mode, gxbb_modes[i].sname)) {
Expand All @@ -511,8 +512,14 @@ int hdmi_outputmode_check(char *mode)
}
}

if (ret)
if (ret) {
printf("hdmitx: outputmode[%s] is invalid\n", mode);
return ret;
}
if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
ret = VIU_MUX_ENCI;
else
ret = VIU_MUX_ENCP;
return ret;
}

Expand Down

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