fix instruction scheduler

dlang · Apr 14, 2013 · abe0cb5 · abe0cb5
1 parent 911f788
commit abe0cb5
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/src/backend/cod4.c b/src/backend/cod4.c
@@ -1599,6 +1599,7 @@ code *cdshass(elem *e,regm_t *pretregs)
               }
               if (oper == OPshlass)
               {       cg = gen(CNIL,&cs);               // cg: SHIFT EA
+                      code_orflag(cg,CFpsw);
                       c = cat(c,cg);
                       getlvalue_msw(&cs);
                       NEWREG(cs.Irm,op2);
@@ -1608,6 +1609,7 @@ code *cdshass(elem *e,regm_t *pretregs)
               else
               {       getlvalue_msw(&cs);
                       cg = gen(CNIL,&cs);
+                      code_orflag(cg,CFpsw);
                       c = cat(c,cg);
                       NEWREG(cs.Irm,op2);
                       getlvalue_lsw(&cs);