bus/pci: add PASID control

[ upstream commit 60ea196 ] Add an internal API to control PASID for a given PCIe device. For kernels when PASID enabled by default it breaks DLB functionality, hence disabling PASID is required for DLB to function properly. PASID capability is not exposed to users hence offset can not be retrieved by rte_pci_find_ext_capability() API. Therefore, API implemented in this commit accepts an offset for PASID with an enable flag which is used to enable/disable PASID. Signed-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>
DPDK · Dec 11, 2023 · 5586a7b · 5586a7b
1 parent dec4b39
commit 5586a7b
Show file tree

Hide file tree

Showing 4 changed files with 29 additions and 0 deletions.
diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
@@ -884,6 +884,16 @@ rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable)
 	return 0;
 }
 
+int
+rte_pci_pasid_set_state(const struct rte_pci_device *dev,
+		off_t offset, bool enable)
+{
+	uint16_t pasid = enable;
+	return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0
+		? -1
+		: 0;
+}
+
 struct rte_pci_bus rte_pci_bus = {
 	.bus = {
 		.scan = rte_pci_scan,

diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
@@ -101,6 +101,20 @@ off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
 __rte_experimental
 int rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable);
 
+/**
+ * Enable/Disable PASID (Process Address Space ID).
+ *
+ * @param dev
+ *   A pointer to a rte_pci_device structure.
+ * @param offset
+ *   Offset of the PASID external capability.
+ * @param enable
+ *   Flag to enable or disable PASID.
+ */
+__rte_internal
+int rte_pci_pasid_set_state(const struct rte_pci_device *dev,
+		off_t offset, bool enable);
+
 /**
  * Read PCI config space.
  *

diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
@@ -27,6 +27,7 @@ INTERNAL {
 	global:
 
 	rte_pci_get_sysfs_path;
+	rte_pci_pasid_set_state;
 	rte_pci_register;
 	rte_pci_unregister;
 };
diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
@@ -45,6 +45,7 @@ extern "C" {
 #define RTE_PCI_EXT_CAP_ID_ERR		0x01	/* Advanced Error Reporting */
 #define RTE_PCI_EXT_CAP_ID_DSN		0x03	/* Device Serial Number */
 #define RTE_PCI_EXT_CAP_ID_SRIOV	0x10	/* SR-IOV*/
+#define RTE_PCI_EXT_CAP_ID_PASID	0x1B    /* Process Address Space ID */
 
 /* Single Root I/O Virtualization */
 #define RTE_PCI_SRIOV_CAP		0x04	/* SR-IOV Capabilities */
@@ -58,6 +59,9 @@ extern "C" {
 #define RTE_PCI_SRIOV_VF_DID		0x1a	/* VF Device ID */
 #define RTE_PCI_SRIOV_SUP_PGSIZE	0x1c	/* Supported Page Sizes */
 
+
+/* Process Address Space ID (RTE_PCI_EXT_CAP_ID_PASID) */
+#define RTE_PCI_PASID_CTRL		0x06    /* PASID control register */
 /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */
 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")