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net/ice: support buffer split in scalar Rx
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Add support for protocol based buffer split in normal Rx
data paths. When the Rx queue is configured with specific protocol type,
packets received will be directly split into protocol header and
payload parts. And the two parts will be put into different mempools.

Currently, protocol based buffer split is not supported in vectorized
paths.

A new API ice_buffer_split_supported_hdr_ptypes_get() has been
introduced, it will return the supported header protocols of ice PMD
to app for splitting.

Signed-off-by: Yuan Wang <yuanx.wang@intel.com>
Signed-off-by: Xuan Ding <xuan.ding@intel.com>
Signed-off-by: Wenxuan Wu <wenxuanx.wu@intel.com>
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@yuanx-wang @ol-andrewr
yuanx-wang authored and ol-andrewr committed Oct 9, 2022
1 parent 52e2e7e commit 629dad3
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Showing 8 changed files with 315 additions and 33 deletions.
2 changes: 1 addition & 1 deletion doc/guides/nics/features.rst
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Expand Up @@ -174,7 +174,7 @@ Supports receiving segmented mbufs.

.. _nic_features_buffer_split:

Buffer Split on Rx
Buffer split on Rx
------------------

Scatters the packets being received on specified boundaries to segmented mbufs.
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1 change: 1 addition & 0 deletions doc/guides/nics/features/default.ini
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Expand Up @@ -23,6 +23,7 @@ Shared Rx queue =
Burst mode info =
Power mgmt address monitor =
MTU update =
Buffer split on Rx =
Scattered Rx =
LRO =
TSO =
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1 change: 1 addition & 0 deletions doc/guides/nics/features/ice.ini
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Expand Up @@ -16,6 +16,7 @@ Queue start/stop = Y
Burst mode info = Y
Power mgmt address monitor = Y
MTU update = Y
Buffer split on Rx = P
Scattered Rx = Y
TSO = Y
Promiscuous mode = Y
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4 changes: 4 additions & 0 deletions doc/guides/rel_notes/release_22_11.rst
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Expand Up @@ -132,6 +132,10 @@ New Features

* Added flow subscription support.

* **Updated Intel ice driver.**

* Added protocol based buffer split support in scalar path.

* **Updated Marvell cnxk driver.**

* Added support for flow action REPRESENTED_PORT.
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58 changes: 56 additions & 2 deletions drivers/net/ice/ice_ethdev.c
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Expand Up @@ -161,6 +161,7 @@ static int ice_timesync_read_time(struct rte_eth_dev *dev,
static int ice_timesync_write_time(struct rte_eth_dev *dev,
const struct timespec *timestamp);
static int ice_timesync_disable(struct rte_eth_dev *dev);
static const uint32_t *ice_buffer_split_supported_hdr_ptypes_get(struct rte_eth_dev *dev);

static const struct rte_pci_id pci_id_ice_map[] = {
{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
Expand Down Expand Up @@ -275,6 +276,7 @@ static const struct eth_dev_ops ice_eth_dev_ops = {
.timesync_write_time = ice_timesync_write_time,
.timesync_disable = ice_timesync_disable,
.tm_ops_get = ice_tm_ops_get,
.buffer_split_supported_hdr_ptypes_get = ice_buffer_split_supported_hdr_ptypes_get,
};

/* store statistics names and its offset in stats structure */
Expand Down Expand Up @@ -3802,7 +3804,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM |
RTE_ETH_RX_OFFLOAD_VLAN_EXTEND |
RTE_ETH_RX_OFFLOAD_RSS_HASH |
RTE_ETH_RX_OFFLOAD_TIMESTAMP;
RTE_ETH_RX_OFFLOAD_TIMESTAMP |
RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT;
dev_info->tx_offload_capa |=
RTE_ETH_TX_OFFLOAD_QINQ_INSERT |
RTE_ETH_TX_OFFLOAD_IPV4_CKSUM |
Expand All @@ -3814,7 +3817,7 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
}

dev_info->rx_queue_offload_capa = 0;
dev_info->rx_queue_offload_capa = RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT;
dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE;

dev_info->reta_size = pf->hash_lut_size;
Expand Down Expand Up @@ -3883,6 +3886,11 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;

dev_info->rx_seg_capa.max_nseg = ICE_RX_MAX_NSEG;
dev_info->rx_seg_capa.multi_pools = 1;
dev_info->rx_seg_capa.offset_allowed = 0;
dev_info->rx_seg_capa.offset_align_log2 = 0;

return 0;
}

Expand Down Expand Up @@ -5960,6 +5968,52 @@ ice_timesync_disable(struct rte_eth_dev *dev)
return 0;
}

static const uint32_t *
ice_buffer_split_supported_hdr_ptypes_get(struct rte_eth_dev *dev __rte_unused)
{
/* Buffer split protocol header capability. */
static const uint32_t ptypes[] = {
/* Non tunneled */
RTE_PTYPE_L2_ETHER,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_L4_SCTP,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_UDP,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_TCP,
RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_L4_SCTP,

/* Tunneled */
RTE_PTYPE_TUNNEL_GRENAT,

RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,

RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,

RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_UDP,
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_TCP,
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_SCTP,

RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_UDP,
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_TCP,
RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN | RTE_PTYPE_INNER_L4_SCTP,

RTE_PTYPE_UNKNOWN
};

return ptypes;
}

static int
ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
struct rte_pci_device *pci_dev)
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