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arm_vm_init.c
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arm_vm_init.c
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/*
* Copyright (c) 2007-2011 Apple Inc. All rights reserved.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_START@
*
* This file contains Original Code and/or Modifications of Original Code
* as defined in and that are subject to the Apple Public Source License
* Version 2.0 (the 'License'). You may not use this file except in
* compliance with the License. The rights granted to you under the License
* may not be used to create, or enable the creation or redistribution of,
* unlawful or unlicensed copies of an Apple operating system, or to
* circumvent, violate, or enable the circumvention or violation of, any
* terms of an Apple operating system software license agreement.
*
* Please obtain a copy of the License at
* http://www.opensource.apple.com/apsl/ and read it before using this file.
*
* The Original Code and all software distributed under the License are
* distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER
* EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,
* INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.
* Please see the License for the specific language governing rights and
* limitations under the License.
*
* @APPLE_OSREFERENCE_LICENSE_HEADER_END@
*/
#include <mach_debug.h>
#include <mach_kdp.h>
#include <debug.h>
#include <mach/vm_types.h>
#include <mach/vm_param.h>
#include <kern/misc_protos.h>
#include <kern/assert.h>
#include <vm/vm_kern.h>
#include <vm/vm_page.h>
#include <vm/pmap.h>
#include <arm64/proc_reg.h>
#include <arm64/lowglobals.h>
#include <arm/cpu_data_internal.h>
#include <arm/misc_protos.h>
#include <pexpert/arm64/boot.h>
#include <libkern/kernel_mach_header.h>
#include <libkern/section_keywords.h>
#if __ARM_KERNEL_PROTECT__
#include <arm/atomic.h>
#endif /* __ARM_KERNEL_PROTECT__ */
#if __ARM_KERNEL_PROTECT__
/*
* If we want to support __ARM_KERNEL_PROTECT__, we need a sufficient amount of
* mappable space preceeding the kernel (as we unmap the kernel by cutting the
* range covered by TTBR1 in half). This must also cover the exception vectors.
*/
static_assert(KERNEL_PMAP_HEAP_RANGE_START > ARM_KERNEL_PROTECT_EXCEPTION_START);
/* The exception vectors and the kernel cannot share root TTEs. */
static_assert((KERNEL_PMAP_HEAP_RANGE_START & ~ARM_TT_ROOT_OFFMASK) > ARM_KERNEL_PROTECT_EXCEPTION_START);
/*
* We must have enough space in the TTBR1_EL1 range to create the EL0 mapping of
* the exception vectors.
*/
static_assert((((~ARM_KERNEL_PROTECT_EXCEPTION_START) + 1) * 2ULL) <= (ARM_TT_ROOT_SIZE + ARM_TT_ROOT_INDEX_MASK));
#endif /* __ARM_KERNEL_PROTECT__ */
#if KASAN
extern vm_offset_t shadow_pbase;
extern vm_offset_t shadow_ptop;
extern vm_offset_t physmap_vbase;
extern vm_offset_t physmap_vtop;
#endif
/*
* Denotes the end of xnu.
*/
extern void *last_kernel_symbol;
/*
* KASLR parameters
*/
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_base;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_top;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kext_base;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kext_top;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_stext;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_etext;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_slide;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_slid_base;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_kernel_slid_top;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_prelink_stext;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_prelink_etext;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_prelink_sdata;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_prelink_edata;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_prelink_sinfo;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_prelink_einfo;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_slinkedit;
SECURITY_READ_ONLY_LATE(vm_offset_t) vm_elinkedit;
/* Used by <mach/arm/vm_param.h> */
SECURITY_READ_ONLY_LATE(unsigned long) gVirtBase;
SECURITY_READ_ONLY_LATE(unsigned long) gPhysBase;
SECURITY_READ_ONLY_LATE(unsigned long) gPhysSize;
/*
* NOTE: mem_size is bogus on large memory machines.
* We will pin it to 0x80000000 if there is more than 2 GB
* This is left only for compatibility and max_mem should be used.
*/
vm_offset_t mem_size; /* Size of actual physical memory present
* minus any performance buffer and possibly
* limited by mem_limit in bytes */
uint64_t mem_actual; /* The "One True" physical memory size
* actually, it's the highest physical
* address + 1 */
uint64_t max_mem; /* Size of physical memory (bytes), adjusted
* by maxmem */
uint64_t sane_size; /* Memory size to use for defaults
* calculations */
/* This no longer appears to be used; kill it? */
addr64_t vm_last_addr = VM_MAX_KERNEL_ADDRESS; /* Highest kernel
* virtual address known
* to the VM system */
SECURITY_READ_ONLY_LATE(static vm_offset_t) segTEXTB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeTEXT;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segDATACONSTB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeDATACONST;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segTEXTEXECB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeTEXTEXEC;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segDATAB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeDATA;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segLINKB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeLINK;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segKLDB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeKLD;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segLASTB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizeLAST;
SECURITY_READ_ONLY_LATE(vm_offset_t) segPRELINKTEXTB;
SECURITY_READ_ONLY_LATE(unsigned long) segSizePRELINKTEXT;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segPLKTEXTEXECB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizePLKTEXTEXEC;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segPLKDATACONSTB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizePLKDATACONST;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segPRELINKDATAB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizePRELINKDATA;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segPLKLLVMCOVB = 0;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizePLKLLVMCOV = 0;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segPLKLINKEDITB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizePLKLINKEDIT;
SECURITY_READ_ONLY_LATE(static vm_offset_t) segPRELINKINFOB;
SECURITY_READ_ONLY_LATE(static unsigned long) segSizePRELINKINFO;
SECURITY_READ_ONLY_LATE(static boolean_t) use_contiguous_hint = TRUE;
SECURITY_READ_ONLY_LATE(unsigned) PAGE_SHIFT_CONST;
SECURITY_READ_ONLY_LATE(vm_offset_t) end_kern;
SECURITY_READ_ONLY_LATE(vm_offset_t) etext;
SECURITY_READ_ONLY_LATE(vm_offset_t) sdata;
SECURITY_READ_ONLY_LATE(vm_offset_t) edata;
vm_offset_t alloc_ptpage(boolean_t map_static);
SECURITY_READ_ONLY_LATE(vm_offset_t) ropage_next;
/*
* Bootstrap the system enough to run with virtual memory.
* Map the kernel's code and data, and allocate the system page table.
* Page_size must already be set.
*
* Parameters:
* first_avail: first available physical page -
* after kernel page tables
* avail_start: PA of first physical page
* avail_end: PA of last physical page
*/
SECURITY_READ_ONLY_LATE(vm_offset_t) first_avail;
SECURITY_READ_ONLY_LATE(vm_offset_t) static_memory_end;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) avail_start;
SECURITY_READ_ONLY_LATE(pmap_paddr_t) avail_end;
#if __ARM_KERNEL_PROTECT__
extern void ExceptionVectorsBase;
extern void ExceptionVectorsEnd;
#endif /* __ARM_KERNEL_PROTECT__ */
#define MEM_SIZE_MAX 0x100000000ULL
#if defined(KERNEL_INTEGRITY_KTRR)
#if __ARM64_TWO_LEVEL_PMAP__
/* We could support this configuration, but it adds memory overhead. */
#error This configuration is not supported
#endif
#endif
/*
* This rounds the given address up to the nearest boundary for a PTE contiguous
* hint.
*/
static vm_offset_t
round_up_pte_hint_address(vm_offset_t address)
{
vm_offset_t hint_size = ARM_PTE_SIZE << ARM_PTE_HINT_ENTRIES_SHIFT;
return ((address + (hint_size - 1)) & ~(hint_size - 1));
}
/* allocate a page for a page table: we support static and dynamic mappings.
*
* returns a virtual address for the allocated page
*
* for static mappings, we allocate from the region ropagetable_begin to ro_pagetable_end-1,
* which is defined in the DATA_CONST segment and will be protected RNX when vm_prot_finalize runs.
*
* for dynamic mappings, we allocate from avail_start, which should remain RWNX.
*/
vm_offset_t alloc_ptpage(boolean_t map_static) {
vm_offset_t vaddr;
#if !(defined(KERNEL_INTEGRITY_KTRR))
map_static = FALSE;
#endif
if (!ropage_next) {
ropage_next = (vm_offset_t)&ropagetable_begin;
}
if (map_static) {
assert(ropage_next < (vm_offset_t)&ropagetable_end);
vaddr = ropage_next;
ropage_next += ARM_PGBYTES;
return vaddr;
} else {
vaddr = phystokv(avail_start);
avail_start += ARM_PGBYTES;
return vaddr;
}
}
#if DEBUG
void dump_kva_l2(vm_offset_t tt_base, tt_entry_t *tt, int indent, uint64_t *rosz_out, uint64_t *rwsz_out);
void dump_kva_l2(vm_offset_t tt_base, tt_entry_t *tt, int indent, uint64_t *rosz_out, uint64_t *rwsz_out) {
unsigned int i;
boolean_t cur_ro, prev_ro = 0;
int start_entry = -1;
tt_entry_t cur, prev = 0;
pmap_paddr_t robegin = kvtophys((vm_offset_t)&ropagetable_begin);
pmap_paddr_t roend = kvtophys((vm_offset_t)&ropagetable_end);
boolean_t tt_static = kvtophys((vm_offset_t)tt) >= robegin &&
kvtophys((vm_offset_t)tt) < roend;
for(i=0; i<TTE_PGENTRIES; i++) {
int tte_type = tt[i] & ARM_TTE_TYPE_MASK;
cur = tt[i] & ARM_TTE_TABLE_MASK;
if (tt_static) {
/* addresses mapped by this entry are static if it is a block mapping,
* or the table was allocated from the RO page table region */
cur_ro = (tte_type == ARM_TTE_TYPE_BLOCK) || (cur >= robegin && cur < roend);
} else {
cur_ro = 0;
}
if ((cur == 0 && prev != 0) || (cur_ro != prev_ro && prev != 0)) { // falling edge
uintptr_t start,end,sz;
start = (uintptr_t)start_entry << ARM_TT_L2_SHIFT;
start += tt_base;
end = ((uintptr_t)i << ARM_TT_L2_SHIFT) - 1;
end += tt_base;
sz = end - start + 1;
printf("%*s0x%08x_%08x-0x%08x_%08x %s (%luMB)\n",
indent*4, "",
(uint32_t)(start >> 32),(uint32_t)start,
(uint32_t)(end >> 32),(uint32_t)end,
prev_ro ? "Static " : "Dynamic",
(sz >> 20));
if (prev_ro) {
*rosz_out += sz;
} else {
*rwsz_out += sz;
}
}
if ((prev == 0 && cur != 0) || cur_ro != prev_ro) { // rising edge: set start
start_entry = i;
}
prev = cur;
prev_ro = cur_ro;
}
}
void dump_kva_space() {
uint64_t tot_rosz=0, tot_rwsz=0;
int ro_ptpages, rw_ptpages;
pmap_paddr_t robegin = kvtophys((vm_offset_t)&ropagetable_begin);
pmap_paddr_t roend = kvtophys((vm_offset_t)&ropagetable_end);
boolean_t root_static = kvtophys((vm_offset_t)cpu_tte) >= robegin &&
kvtophys((vm_offset_t)cpu_tte) < roend;
uint64_t kva_base = ~((1ULL << (64 - T1SZ_BOOT)) - 1);
printf("Root page table: %s\n", root_static ? "Static" : "Dynamic");
#if !__ARM64_TWO_LEVEL_PMAP__
for(unsigned int i=0; i<TTE_PGENTRIES; i++) {
pmap_paddr_t cur;
boolean_t cur_ro;
uintptr_t start,end;
uint64_t rosz = 0, rwsz = 0;
if ((cpu_tte[i] & ARM_TTE_VALID) == 0)
continue;
cur = cpu_tte[i] & ARM_TTE_TABLE_MASK;
start = (uint64_t)i << ARM_TT_L1_SHIFT;
start = start + kva_base;
end = start + (ARM_TT_L1_SIZE - 1);
cur_ro = cur >= robegin && cur < roend;
printf("0x%08x_%08x-0x%08x_%08x %s\n",
(uint32_t)(start >> 32),(uint32_t)start,
(uint32_t)(end >> 32),(uint32_t)end,
cur_ro ? "Static " : "Dynamic");
dump_kva_l2(start, (tt_entry_t*)phystokv(cur), 1, &rosz, &rwsz);
tot_rosz += rosz;
tot_rwsz += rwsz;
}
#else
dump_kva_l2(kva_base, cpu_tte, 0, &tot_rosz, &tot_rwsz);
#endif /* !_ARM64_TWO_LEVEL_PMAP__ */
printf("L2 Address space mapped: Static %lluMB Dynamic %lluMB Total %lluMB\n",
tot_rosz >> 20,
tot_rwsz >> 20,
(tot_rosz >> 20) + (tot_rwsz >> 20));
ro_ptpages = (int)((ropage_next - (vm_offset_t)&ropagetable_begin) >> ARM_PGSHIFT);
rw_ptpages = (int)(lowGlo.lgStaticSize >> ARM_PGSHIFT);
printf("Pages used: static %d dynamic %d\n", ro_ptpages, rw_ptpages);
}
#endif /* DEBUG */
#if __ARM_KERNEL_PROTECT__
/*
* arm_vm_map:
* root_ttp: The kernel virtual address for the root of the target page tables
* vaddr: The target virtual address
* pte: A page table entry value (may be ARM_PTE_EMPTY)
*
* This function installs pte at vaddr in root_ttp. Any page table pages needed
* to install pte will be allocated by this function.
*/
static void
arm_vm_map(tt_entry_t * root_ttp, vm_offset_t vaddr, pt_entry_t pte)
{
vm_offset_t ptpage = 0;
tt_entry_t * ttp = root_ttp;
#if !__ARM64_TWO_LEVEL_PMAP__
tt_entry_t * l1_ttep = NULL;
tt_entry_t l1_tte = 0;
#endif
tt_entry_t * l2_ttep = NULL;
tt_entry_t l2_tte = 0;
pt_entry_t * ptep = NULL;
pt_entry_t cpte = 0;
/*
* Walk the target page table to find the PTE for the given virtual
* address. Allocate any page table pages needed to do this.
*/
#if !__ARM64_TWO_LEVEL_PMAP__
l1_ttep = ttp + ((vaddr & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT);
l1_tte = *l1_ttep;
if (l1_tte == ARM_TTE_EMPTY) {
ptpage = alloc_ptpage(TRUE);
bzero((void *)ptpage, ARM_PGBYTES);
l1_tte = kvtophys(ptpage);
l1_tte &= ARM_TTE_TABLE_MASK;
l1_tte |= ARM_TTE_VALID | ARM_TTE_TYPE_TABLE;
*l1_ttep = l1_tte;
ptpage = 0;
}
ttp = (tt_entry_t *)phystokv(l1_tte & ARM_TTE_TABLE_MASK);
#endif
l2_ttep = ttp + ((vaddr & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT);
l2_tte = *l2_ttep;
if (l2_tte == ARM_TTE_EMPTY) {
ptpage = alloc_ptpage(TRUE);
bzero((void *)ptpage, ARM_PGBYTES);
l2_tte = kvtophys(ptpage);
l2_tte &= ARM_TTE_TABLE_MASK;
l2_tte |= ARM_TTE_VALID | ARM_TTE_TYPE_TABLE;
*l2_ttep = l2_tte;
ptpage = 0;
}
ttp = (tt_entry_t *)phystokv(l2_tte & ARM_TTE_TABLE_MASK);
ptep = ttp + ((vaddr & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT);
cpte = *ptep;
/*
* If the existing PTE is not empty, then we are replacing a valid
* mapping.
*/
if (cpte != ARM_PTE_EMPTY) {
panic("%s: cpte=%#llx is not empty, "
"vaddr=%#lx, pte=%#llx",
__FUNCTION__, cpte,
vaddr, pte);
}
*ptep = pte;
}
/*
* arm_vm_kernel_el0_map:
* vaddr: The target virtual address
* pte: A page table entry value (may be ARM_PTE_EMPTY)
*
* This function installs pte at vaddr for the EL0 kernel mappings.
*/
static void
arm_vm_kernel_el0_map(vm_offset_t vaddr, pt_entry_t pte)
{
/* Calculate where vaddr will be in the EL1 kernel page tables. */
vm_offset_t kernel_pmap_vaddr = vaddr - ((ARM_TT_ROOT_INDEX_MASK + ARM_TT_ROOT_SIZE) / 2ULL);
arm_vm_map(cpu_tte, kernel_pmap_vaddr, pte);
}
/*
* arm_vm_kernel_el1_map:
* vaddr: The target virtual address
* pte: A page table entry value (may be ARM_PTE_EMPTY)
*
* This function installs pte at vaddr for the EL1 kernel mappings.
*/
static void
arm_vm_kernel_el1_map(vm_offset_t vaddr, pt_entry_t pte) {
arm_vm_map(cpu_tte, vaddr, pte);
}
/*
* arm_vm_kernel_pte:
* vaddr: The target virtual address
*
* This function returns the PTE value for the given vaddr from the kernel page
* tables. If the region has been been block mapped, we return what an
* equivalent PTE value would be (as regards permissions and flags). We also
* remove the HINT bit (as we are not necessarily creating contiguous mappings.
*/
static pt_entry_t
arm_vm_kernel_pte(vm_offset_t vaddr)
{
tt_entry_t * ttp = cpu_tte;
tt_entry_t * ttep = NULL;
tt_entry_t tte = 0;
pt_entry_t * ptep = NULL;
pt_entry_t pte = 0;
#if !__ARM64_TWO_LEVEL_PMAP__
ttep = ttp + ((vaddr & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT);
tte = *ttep;
assert(tte & ARM_TTE_VALID);
if ((tte & ARM_TTE_TYPE_MASK) == ARM_TTE_TYPE_BLOCK) {
/* This is a block mapping; return the equivalent PTE value. */
pte = (pt_entry_t)(tte & ~ARM_TTE_TYPE_MASK);
pte |= ARM_PTE_TYPE_VALID;
pte |= vaddr & ((ARM_TT_L1_SIZE - 1) & ARM_PTE_PAGE_MASK);
pte &= ~ARM_PTE_HINT_MASK;
return pte;
}
ttp = (tt_entry_t *)phystokv(tte & ARM_TTE_TABLE_MASK);
#endif
ttep = ttp + ((vaddr & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT);
tte = *ttep;
assert(tte & ARM_TTE_VALID);
if ((tte & ARM_TTE_TYPE_MASK) == ARM_TTE_TYPE_BLOCK) {
/* This is a block mapping; return the equivalent PTE value. */
pte = (pt_entry_t)(tte & ~ARM_TTE_TYPE_MASK);
pte |= ARM_PTE_TYPE_VALID;
pte |= vaddr & ((ARM_TT_L2_SIZE - 1) & ARM_PTE_PAGE_MASK);
pte &= ~ARM_PTE_HINT_MASK;
return pte;
}
ttp = (tt_entry_t *)phystokv(tte & ARM_TTE_TABLE_MASK);
ptep = ttp + ((vaddr & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT);
pte = *ptep;
pte &= ~ARM_PTE_HINT_MASK;
return pte;
}
/*
* arm_vm_prepare_kernel_el0_mappings:
* alloc_only: Indicates if PTE values should be copied from the EL1 kernel
* mappings.
*
* This function expands the kernel page tables to support the EL0 kernel
* mappings, and conditionally installs the PTE values for the EL0 kernel
* mappings (if alloc_only is false).
*/
static void
arm_vm_prepare_kernel_el0_mappings(bool alloc_only)
{
pt_entry_t pte = 0;
vm_offset_t start = ((vm_offset_t)&ExceptionVectorsBase) & ~PAGE_MASK;
vm_offset_t end = (((vm_offset_t)&ExceptionVectorsEnd) + PAGE_MASK) & ~PAGE_MASK;
vm_offset_t cur = 0;
vm_offset_t cur_fixed = 0;
/* Expand for/map the exceptions vectors in the EL0 kernel mappings. */
for (cur = start, cur_fixed = ARM_KERNEL_PROTECT_EXCEPTION_START; cur < end; cur += ARM_PGBYTES, cur_fixed += ARM_PGBYTES) {
/*
* We map the exception vectors at a different address than that
* of the kernelcache to avoid sharing page table pages with the
* kernelcache (as this may cause issues with TLB caching of
* page table pages.
*/
if (!alloc_only) {
pte = arm_vm_kernel_pte(cur);
}
arm_vm_kernel_el1_map(cur_fixed, pte);
arm_vm_kernel_el0_map(cur_fixed, pte);
}
__builtin_arm_dmb(DMB_ISH);
__builtin_arm_isb(ISB_SY);
if (!alloc_only) {
/*
* If we have created the alternate exception vector mappings,
* the boot CPU may now switch over to them.
*/
set_vbar_el1(ARM_KERNEL_PROTECT_EXCEPTION_START);
__builtin_arm_isb(ISB_SY);
}
}
/*
* arm_vm_populate_kernel_el0_mappings:
*
* This function adds all required mappings to the EL0 kernel mappings.
*/
static void
arm_vm_populate_kernel_el0_mappings(void)
{
arm_vm_prepare_kernel_el0_mappings(FALSE);
}
/*
* arm_vm_expand_kernel_el0_mappings:
*
* This function expands the kernel page tables to accomodate the EL0 kernel
* mappings.
*/
static void
arm_vm_expand_kernel_el0_mappings(void)
{
arm_vm_prepare_kernel_el0_mappings(TRUE);
}
#endif /* __ARM_KERNEL_PROTECT__ */
#if defined(KERNEL_INTEGRITY_KTRR)
extern void bootstrap_instructions;
/*
* arm_replace_identity_map takes the V=P map that we construct in start.s
* and repurposes it in order to have it map only the page we need in order
* to turn on the MMU. This prevents us from running into issues where
* KTRR will cause us to fault on executable block mappings that cross the
* KTRR boundary.
*/
static void arm_replace_identity_map(boot_args * args)
{
vm_offset_t addr;
pmap_paddr_t paddr;
#if !__ARM64_TWO_LEVEL_PMAP__
pmap_paddr_t l1_ptp_phys = 0;
tt_entry_t *l1_ptp_virt = NULL;
tt_entry_t *tte1 = NULL;
#endif
pmap_paddr_t l2_ptp_phys = 0;
tt_entry_t *l2_ptp_virt = NULL;
tt_entry_t *tte2 = NULL;
pmap_paddr_t l3_ptp_phys = 0;
pt_entry_t *l3_ptp_virt = NULL;
pt_entry_t *ptep = NULL;
addr = ((vm_offset_t)&bootstrap_instructions) & ~ARM_PGMASK;
paddr = kvtophys(addr);
/*
* The V=P page tables (at the time this comment was written) start
* after the last bit of kernel data, and consist of 1 to 2 pages.
* Grab references to those pages, and allocate an L3 page.
*/
#if !__ARM64_TWO_LEVEL_PMAP__
l1_ptp_phys = args->topOfKernelData;
l1_ptp_virt = (tt_entry_t *)phystokv(l1_ptp_phys);
tte1 = &l1_ptp_virt[(((paddr) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT)];
l2_ptp_phys = l1_ptp_phys + ARM_PGBYTES;
#else
l2_ptp_phys = args->topOfKernelData;
#endif
l2_ptp_virt = (tt_entry_t *)phystokv(l2_ptp_phys);
tte2 = &l2_ptp_virt[(((paddr) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)];
l3_ptp_virt = (pt_entry_t *)alloc_ptpage(FALSE);
l3_ptp_phys = kvtophys((vm_offset_t)l3_ptp_virt);
ptep = &l3_ptp_virt[(((paddr) & ARM_TT_L3_INDEX_MASK) >> ARM_TT_L3_SHIFT)];
/*
* Replace the large V=P mapping with a mapping that provides only the
* mappings needed to turn on the MMU.
*/
#if !__ARM64_TWO_LEVEL_PMAP__
bzero(l1_ptp_virt, ARM_PGBYTES);
*tte1 = ARM_TTE_BOOT_TABLE | (l2_ptp_phys & ARM_TTE_TABLE_MASK);
#endif
bzero(l2_ptp_virt, ARM_PGBYTES);
*tte2 = ARM_TTE_BOOT_TABLE | (l3_ptp_phys & ARM_TTE_TABLE_MASK);
*ptep = (paddr & ARM_PTE_MASK) |
ARM_PTE_TYPE_VALID |
ARM_PTE_SH(SH_OUTER_MEMORY) |
ARM_PTE_ATTRINDX(CACHE_ATTRINDX_WRITEBACK) |
ARM_PTE_AF |
ARM_PTE_AP(AP_RONA) |
ARM_PTE_NX;
}
#endif /* defined(KERNEL_INTEGRITY_KTRR)*/
/*
* arm_vm_page_granular_helper updates protections at the L3 level. It will (if
* neccessary) allocate a page for the L3 table and update the corresponding L2
* entry. Then, it will iterate over the L3 table, updating protections as necessary.
* This expects to be invoked on a L2 entry or sub L2 entry granularity, so this should
* not be invoked from a context that does not do L2 iteration separately (basically,
* don't call this except from arm_vm_page_granular_prot).
*/
static void
arm_vm_page_granular_helper(vm_offset_t start, vm_offset_t _end, vm_offset_t va,
int pte_prot_APX, int pte_prot_XN, int forceCoarse,
pt_entry_t **deferred_pte, pt_entry_t *deferred_ptmp)
{
if (va & ARM_TT_L2_OFFMASK) { /* ragged edge hanging over a ARM_TT_L2_SIZE boundary */
#if __ARM64_TWO_LEVEL_PMAP__
tt_entry_t *tte2;
#else
tt_entry_t *tte1, *tte2;
#endif
tt_entry_t tmplate;
pmap_paddr_t pa;
pt_entry_t *ppte, *recursive_pte = NULL, ptmp, recursive_ptmp = 0;
addr64_t ppte_phys;
unsigned i;
va &= ~ARM_TT_L2_OFFMASK;
pa = va - gVirtBase + gPhysBase;
#if __ARM64_TWO_LEVEL_PMAP__
tte2 = &cpu_tte[(((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)];
#else
tte1 = &cpu_tte[(((va) & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT)];
tte2 = &((tt_entry_t*) phystokv((*tte1) & ARM_TTE_TABLE_MASK))[(((va) & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)];
#endif
tmplate = *tte2;
if (ARM_TTE_TYPE_TABLE == (tmplate & ARM_TTE_TYPE_MASK)) {
/* pick up the existing page table. */
ppte = (pt_entry_t *)phystokv((tmplate & ARM_TTE_TABLE_MASK));
} else {
// TTE must be reincarnated COARSE.
ppte = (pt_entry_t*)alloc_ptpage(TRUE);
ppte_phys = kvtophys((vm_offset_t)ppte);
pmap_init_pte_static_page(kernel_pmap, ppte, pa);
*tte2 = pa_to_tte(ppte_phys) | ARM_TTE_TYPE_TABLE | ARM_TTE_VALID;
}
/* Apply the desired protections to the specified page range */
for (i = 0; i <= (ARM_TT_L3_INDEX_MASK>>ARM_TT_L3_SHIFT); i++) {
if ((start <= va) && (va < _end)) {
ptmp = pa | ARM_PTE_AF | ARM_PTE_SH(SH_OUTER_MEMORY) | ARM_PTE_TYPE;
ptmp = ptmp | ARM_PTE_ATTRINDX(CACHE_ATTRINDX_DEFAULT);
ptmp = ptmp | ARM_PTE_AP(pte_prot_APX);
ptmp = ptmp | ARM_PTE_NX;
#if __ARM_KERNEL_PROTECT__
ptmp = ptmp | ARM_PTE_NG;
#endif /* __ARM_KERNEL_PROTECT__ */
if (pte_prot_XN) {
ptmp = ptmp | ARM_PTE_PNX;
}
/*
* If we can, apply the contiguous hint to this range. The hint is
* applicable if we are not trying to create per-page mappings and
* if the current address falls within a hint-sized range that will
* be fully covered by this mapping request.
*/
if ((va >= round_up_pte_hint_address(start)) && (round_up_pte_hint_address(va + 1) < _end) &&
!forceCoarse && use_contiguous_hint) {
ptmp |= ARM_PTE_HINT;
}
if ((pt_entry_t*)(phystokv(pa)) == ppte) {
assert(recursive_pte == NULL);
/* This assert should be reenabled as part of rdar://problem/30149465 */
assert(!forceCoarse);
recursive_pte = &ppte[i];
recursive_ptmp = ptmp;
} else if ((deferred_pte != NULL) && (&ppte[i] == &recursive_pte[1])) {
assert(*deferred_pte == NULL);
assert(deferred_ptmp != NULL);
*deferred_pte = &ppte[i];
*deferred_ptmp = ptmp;
} else {
ppte[i] = ptmp;
}
}
va += ARM_PGBYTES;
pa += ARM_PGBYTES;
}
if (recursive_pte != NULL)
*recursive_pte = recursive_ptmp;
}
}
/*
* arm_vm_page_granular_prot updates protections by iterating over the L2 entries and
* changing them. If a particular chunk necessitates L3 entries (for reasons of
* alignment or length, or an explicit request that the entry be fully expanded), we
* hand off to arm_vm_page_granular_helper to deal with the L3 chunk of the logic.
*
* Note that counterintuitively a forceCoarse request is a request to expand the entries
* out to L3, i.e. to make *finer* grained mappings. That comes from historical arm32
* nomenclature in which the 4K granule is "coarse" vs. the 1K "fine" granule (which we
* don't use).
*/
static void
arm_vm_page_granular_prot(vm_offset_t start, unsigned long size,
int tte_prot_XN, int pte_prot_APX, int pte_prot_XN, int forceCoarse)
{
pt_entry_t *deferred_pte = NULL, deferred_ptmp = 0;
vm_offset_t _end = start + size;
vm_offset_t align_start = (start + ARM_TT_L2_OFFMASK) & ~ARM_TT_L2_OFFMASK;
if (size == 0x0UL)
return;
if (align_start > _end) {
arm_vm_page_granular_helper(start, _end, start, pte_prot_APX, pte_prot_XN, forceCoarse, NULL, NULL);
return;
}
arm_vm_page_granular_helper(start, align_start, start, pte_prot_APX, pte_prot_XN, forceCoarse, &deferred_pte, &deferred_ptmp);
while ((_end - align_start) >= ARM_TT_L2_SIZE) {
if (forceCoarse)
arm_vm_page_granular_helper(align_start, align_start+ARM_TT_L2_SIZE, align_start + 1,
pte_prot_APX, pte_prot_XN, forceCoarse, NULL, NULL);
else {
#if __ARM64_TWO_LEVEL_PMAP__
tt_entry_t *tte2;
#else
tt_entry_t *tte1, *tte2;
#endif
tt_entry_t tmplate;
#if __ARM64_TWO_LEVEL_PMAP__
tte2 = &cpu_tte[((align_start & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)];
#else
tte1 = &cpu_tte[((align_start & ARM_TT_L1_INDEX_MASK) >> ARM_TT_L1_SHIFT)];
tte2 = &((tt_entry_t*) phystokv((*tte1) & ARM_TTE_TABLE_MASK))[((align_start & ARM_TT_L2_INDEX_MASK) >> ARM_TT_L2_SHIFT)];
#endif
tmplate = *tte2;
tmplate = (tmplate & ~ARM_TTE_BLOCK_APMASK) | ARM_TTE_BLOCK_AP(pte_prot_APX);
tmplate = tmplate | ARM_TTE_BLOCK_NX;
#if __ARM_KERNEL_PROTECT__
tmplate = tmplate | ARM_TTE_BLOCK_NG;
#endif /* __ARM_KERNEL_PROTECT__ */
if (tte_prot_XN)
tmplate = tmplate | ARM_TTE_BLOCK_PNX;
*tte2 = tmplate;
}
align_start += ARM_TT_L2_SIZE;
}
if (align_start < _end)
arm_vm_page_granular_helper(align_start, _end, _end, pte_prot_APX, pte_prot_XN, forceCoarse, &deferred_pte, &deferred_ptmp);
if (deferred_pte != NULL)
*deferred_pte = deferred_ptmp;
}
static inline void
arm_vm_page_granular_RNX(vm_offset_t start, unsigned long size, int forceCoarse)
{
arm_vm_page_granular_prot(start, size, 1, AP_RONA, 1, forceCoarse);
}
static inline void
arm_vm_page_granular_ROX(vm_offset_t start, unsigned long size, int forceCoarse)
{
arm_vm_page_granular_prot(start, size, 0, AP_RONA, 0, forceCoarse);
}
static inline void
arm_vm_page_granular_RWNX(vm_offset_t start, unsigned long size, int forceCoarse)
{
arm_vm_page_granular_prot(start, size, 1, AP_RWNA, 1, forceCoarse);
}
static inline void
arm_vm_page_granular_RWX(vm_offset_t start, unsigned long size, int forceCoarse)
{
arm_vm_page_granular_prot(start, size, 0, AP_RWNA, 0, forceCoarse);
}
void
arm_vm_prot_init(boot_args * args)
{
/*
* Enforce W^X protections on sections that have been identified so far. This will be
* further refined for each KEXT's TEXT and DATA segments in readPrelinkedExtensions()
*/
bool use_small_page_mappings = FALSE;
/*
* First off, we'll create mappings for any physical memory preceeding the kernel TEXT.
* This is memory that we want to give to the VM; this will be accomplished through an
* ml_static_mfree call in arm_vm_prot_finalize. This allows the pmap/vm bootstrap
* routines to assume they will have a physically contiguous chunk of memory to deal
* with during bootstrap, while reclaiming this memory later.
*/
arm_vm_page_granular_RWNX(gVirtBase, segPRELINKTEXTB - gVirtBase, use_small_page_mappings); // Memory for the VM
/* Map coalesced kext TEXT segment RWNX for now */
arm_vm_page_granular_RWNX(segPRELINKTEXTB, segSizePRELINKTEXT, FALSE); // Refined in OSKext::readPrelinkedExtensions
/* Map coalesced kext DATA_CONST segment RWNX (could be empty) */
arm_vm_page_granular_RWNX(segPLKDATACONSTB, segSizePLKDATACONST, FALSE); // Refined in OSKext::readPrelinkedExtensions
/* Map coalesced kext TEXT_EXEC segment RWX (could be empty) */
arm_vm_page_granular_ROX(segPLKTEXTEXECB, segSizePLKTEXTEXEC, FALSE); // Refined in OSKext::readPrelinkedExtensions
/* if new segments not present, set space between PRELINK_TEXT and xnu TEXT to RWNX
* otherwise we no longer expecting any space between the coalesced kext read only segments and xnu rosegments
*/
if (!segSizePLKDATACONST && !segSizePLKTEXTEXEC) {
arm_vm_page_granular_RWNX(segPRELINKTEXTB + segSizePRELINKTEXT, segTEXTB - (segPRELINKTEXTB + segSizePRELINKTEXT), FALSE);
} else {
/*
* If we have the new segments, we should still protect the gap between kext
* read-only pages and kernel read-only pages, in the event that this gap
* exists.
*/
if ((segPLKDATACONSTB + segSizePLKDATACONST) < segTEXTB) {
arm_vm_page_granular_RWNX(segPLKDATACONSTB + segSizePLKDATACONST, segTEXTB - (segPLKDATACONSTB + segSizePLKDATACONST), FALSE);
}
}
/*
* Protection on kernel text is loose here to allow shenanigans early on. These
* protections are tightened in arm_vm_prot_finalize(). This is necessary because
* we currently patch LowResetVectorBase in cpu.c.
*
* TEXT segment contains mach headers and other non-executable data. This will become RONX later.
*/
arm_vm_page_granular_RNX(segTEXTB, segSizeTEXT, FALSE);
/* Can DATACONST start out and stay RNX?
* NO, stuff in this segment gets modified during startup (viz. mac_policy_init()/mac_policy_list)
* Make RNX in prot_finalize
*/
arm_vm_page_granular_RWNX(segDATACONSTB, segSizeDATACONST, FALSE);
/* TEXTEXEC contains read only executable code: becomes ROX in prot_finalize */
arm_vm_page_granular_RWX(segTEXTEXECB, segSizeTEXTEXEC, FALSE);
/* DATA segment will remain RWNX */
arm_vm_page_granular_RWNX(segDATAB, segSizeDATA, FALSE);
arm_vm_page_granular_ROX(segKLDB, segSizeKLD, FALSE);
arm_vm_page_granular_RWNX(segLINKB, segSizeLINK, FALSE);
arm_vm_page_granular_ROX(segLASTB, segSizeLAST, FALSE); // __LAST may be empty, but we cannot assume this
arm_vm_page_granular_RWNX(segPRELINKDATAB, segSizePRELINKDATA, FALSE); // Prelink __DATA for kexts (RW data)
if (segSizePLKLLVMCOV > 0)
arm_vm_page_granular_RWNX(segPLKLLVMCOVB, segSizePLKLLVMCOV, FALSE); // LLVM code coverage data
arm_vm_page_granular_RWNX(segPLKLINKEDITB, segSizePLKLINKEDIT, use_small_page_mappings); // Coalesced kext LINKEDIT segment
arm_vm_page_granular_RWNX(segPRELINKINFOB, segSizePRELINKINFO, FALSE); /* PreLinkInfoDictionary */
arm_vm_page_granular_RWNX(end_kern, phystokv(args->topOfKernelData) - end_kern, use_small_page_mappings); /* Device Tree, RAM Disk (if present), bootArgs */
/*
* This is offset by 4 pages to make room for the boot page tables; we could probably
* include them in the overall mapping, but we'll be paranoid for now.
*/
vm_offset_t extra = 0;
#if KASAN
/* add the KASAN stolen memory to the physmap */
extra = shadow_ptop - shadow_pbase;
/* record the extent of the physmap */
physmap_vbase = phystokv(args->topOfKernelData) + ARM_PGBYTES * 4;
physmap_vtop = static_memory_end;
#endif
arm_vm_page_granular_RNX(phystokv(args->topOfKernelData), ARM_PGBYTES * 4, FALSE); // Boot page tables; they should not be mutable.
arm_vm_page_granular_RWNX(phystokv(args->topOfKernelData) + ARM_PGBYTES * 4,
extra + static_memory_end - ((phystokv(args->topOfKernelData) + ARM_PGBYTES * 4)), use_small_page_mappings); // rest of physmem
}
void
arm_vm_prot_finalize(boot_args * args)
{
#pragma unused(args)
/*
* At this point, we are far enough along in the boot process that it will be
* safe to free up all of the memory preceeding the kernel. It may in fact
* be safe to do this earlier.
*
* This keeps the memory in the V-to-P mapping, but advertises it to the VM
* as usable.
*/
/*
* if old style PRELINK segment exists, free memory before it, and after it before XNU text
* otherwise we're dealing with a new style kernel cache, so we should just free the
* memory before PRELINK_TEXT segment, since the rest of the KEXT read only data segments
* should be immediately followed by XNU's TEXT segment
*/
ml_static_mfree(gVirtBase, segPRELINKTEXTB - gVirtBase);
if (!segSizePLKDATACONST && !segSizePLKTEXTEXEC) {
/* If new segments not present, PRELINK_TEXT is not dynamically sized, free DRAM between it and xnu TEXT */
ml_static_mfree(segPRELINKTEXTB + segSizePRELINKTEXT, segTEXTB - (segPRELINKTEXTB + segSizePRELINKTEXT));
}
/*
* LowResetVectorBase patching should be done by now, so tighten executable