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| # This is a gitignore file automatically generated by digilent_vivado_checkin.tcl | ||
| # Remove this comment block when editing this file; the file will not be overwritten unless deleted | ||
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| # root | ||
| /* | ||
| !.gitignore | ||
| !.gitmodules | ||
| !README.md | ||
| !LICENSE | ||
| !project_info.tcl | ||
| !proj/ | ||
| !repo/ | ||
| !sdk/ | ||
| !src/ | ||
| !digilent-vivado-scripts/ | ||
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| # vivado workspace | ||
| proj/* | ||
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| # ip repository | ||
| repo/** | ||
| !repo/vivado-library | ||
| repo/vivado-library/** | ||
| !repo/local | ||
| !repo/local/** | ||
| !repo/cache | ||
| repo/cache/** | ||
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| # version controlled sources | ||
| src/** | ||
| !src/bd | ||
| src/bd/** | ||
| !src/bd/*.tcl | ||
| !src/constraints | ||
| src/constraints/** | ||
| !src/constraints/*.xdc | ||
| !src/hdl | ||
| src/hdl/** | ||
| !src/hdl/*.v | ||
| !src/hdl/*.vhd | ||
| !src/ip | ||
| !src/ip/* | ||
| src/ip/*/** | ||
| !src/ip/**/*.xci | ||
| !src/other | ||
| !src/other/** | ||
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| # sdk application sources | ||
| sdk/** | ||
| !sdk/appsrc | ||
| !sdk/appsrc/** | ||
|
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| # maintain required directories | ||
| !**/.keep |
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| [submodule "digilent-vivado-scripts"] | ||
| path = digilent-vivado-scripts | ||
| url = https://github.com/Digilent/digilent-vivado-scripts | ||
| [submodule "repo/vivado-library"] | ||
| path = repo/vivado-library | ||
| url = https://github.com/Digilent/vivado-library |
Submodule digilent-vivado-scripts
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| # This is an automatically generated file used by digilent_vivado_checkout.tcl to set project options | ||
| proc set_digilent_project_properties {proj_name} { | ||
| set project_obj [get_projects $proj_name] | ||
| set_property "part" "xc7z020clg400-1" $project_obj | ||
| set_property "board_part" "digilentinc.com:arty-z7-20:part0:1.0" $project_obj | ||
| set_property "default_lib" "xil_defaultlib" $project_obj | ||
| set_property "simulator_language" "Mixed" $project_obj | ||
| set_property "target_language" "Verilog" $project_obj | ||
| } |
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| proc init { cellpath otherInfo } { | ||
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| set cell_handle [get_bd_cells $cellpath] | ||
| set all_busif [get_bd_intf_pins $cellpath/*] | ||
| set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] | ||
| set full_sbusif_list [list ] | ||
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| foreach busif $all_busif { | ||
| if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } { | ||
| set busif_param_list [list] | ||
| set busif_name [get_property NAME $busif] | ||
| if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } { | ||
| continue | ||
| } | ||
| foreach tparam $axi_standard_param_list { | ||
| lappend busif_param_list "C_${busif_name}_${tparam}" | ||
| } | ||
| bd::mark_propagate_only $cell_handle $busif_param_list | ||
| } | ||
| } | ||
| } | ||
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| proc pre_propagate {cellpath otherInfo } { | ||
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| set cell_handle [get_bd_cells $cellpath] | ||
| set all_busif [get_bd_intf_pins $cellpath/*] | ||
| set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] | ||
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| foreach busif $all_busif { | ||
| if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { | ||
| continue | ||
| } | ||
| if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } { | ||
| continue | ||
| } | ||
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| set busif_name [get_property NAME $busif] | ||
| foreach tparam $axi_standard_param_list { | ||
| set busif_param_name "C_${busif_name}_${tparam}" | ||
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| set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] | ||
| set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] | ||
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| if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { | ||
| if { $val_on_cell != "" } { | ||
| set_property CONFIG.${tparam} $val_on_cell $busif | ||
| } | ||
| } | ||
| } | ||
| } | ||
| } | ||
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| proc propagate {cellpath otherInfo } { | ||
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| set cell_handle [get_bd_cells $cellpath] | ||
| set all_busif [get_bd_intf_pins $cellpath/*] | ||
| set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH] | ||
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| foreach busif $all_busif { | ||
| if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } { | ||
| continue | ||
| } | ||
| if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } { | ||
| continue | ||
| } | ||
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| set busif_name [get_property NAME $busif] | ||
| foreach tparam $axi_standard_param_list { | ||
| set busif_param_name "C_${busif_name}_${tparam}" | ||
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| set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif] | ||
| set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle] | ||
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| if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } { | ||
| #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values.. | ||
| if { $val_on_cell_intf_pin != "" } { | ||
| set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle | ||
| } | ||
| } | ||
| } | ||
| } | ||
| } | ||
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