simple: simple audio overlays for bclk_int_div

Specify a bclk_integer_divisor preference for multiples of 8k rates
using the msperl simple-card framework via dt overlay.

40/80 bclk_ratio using dtoverlay=simple-bclk-int-div-40-80
50/100 bclk_ratio using dtoverlay=simple-bclk-int-div-50-100

Typically would be used in conjunction with simple-es9023-audio overlay.

eg. dtoverlay=simple-es9023-audio,card_name="Akkordion"
    dtoverlay=simple-bclk-int-div-40-80

Version 2, add an overlay, simple-bclk-64fs-overlay.dts, for fixed 64fs
bclk_ratio, regardless of data bit depth.

Signed-off-by: DigitalDreamtime <clive.messer@digitaldreamtime.co.uk>

arch/arm/boot/dts/overlays/Makefile

@@ -88,6 +88,9 @@ dtbo-$(RPI_DT_OVERLAYS) += sdhost.dtbo
 dtbo-$(RPI_DT_OVERLAYS) += sdio.dtbo
 dtbo-$(RPI_DT_OVERLAYS) += sdio-1bit.dtbo
 dtbo-$(RPI_DT_OVERLAYS) += sdtweak.dtbo
+dtbo-$(RPI_DT_OVERLAYS) += simple-bclk-int-div-40-80.dtbo
+dtbo-$(RPI_DT_OVERLAYS) += simple-bclk-int-div-50-100.dtbo
+dtbo-$(RPI_DT_OVERLAYS) += simple-bclk-64fs.dtbo
 dtbo-$(RPI_DT_OVERLAYS) += simple-es9023-audio.dtbo
 dtbo-$(RPI_DT_OVERLAYS) += simple-pcm5102a-audio.dtbo
 dtbo-$(RPI_DT_OVERLAYS) += smi.dtbo

arch/arm/boot/dts/overlays/README

@@ -1163,6 +1163,32 @@ Params: overclock_50            Clock (in MHz) to use when the MMC framework
         debug                   Enable debug output (default off)
 
 
+Name:   simple-bclk-64fs
+Info:   Use a "fixed" 64fs bclk_ratio for 2 channel, 32/24/16 bit audio.
+Load:   dtoverlay=simple-bclk-64fs
+Params: <None>
+
+
+Name:   simple-bclk-int-div-40-80
+Info:   Specify a bclk_integer_divisor preference for multiples of 8k rates
+        Use bclk_ratio=40 for S16_LE and bclk_ratio=80 for S24_LE and S32_LE
+        formats when the media sample rate is a multiple of 8000kHz and less
+        than 192kHz, which allows the use of the OSC with integer divider
+        rather than PLL with fractional (MASH) divider.
+Load:   dtoverlay=simple-bclk-int-div-40-80
+Params: <None>
+
+
+Name:   simple-bclk-int-div-50-100
+Info:   Specify a bclk_integer_divisor preference for multiples of 8k rates
+        Use bclk_ratio=50 for S16_LE and bclk_ratio=100 for S24_LE and S32_LE
+        formats when the media sample rate is a multiple of 8000kHz and less
+        than 192kHz, which allows the use of the OSC with integer divider
+        rather than PLL with fractional (MASH) divider.
+Load:   dtoverlay=simple-bclk-int-div-50-100
+Params: <None>
+
+
 Name:   simple-es9023-audio
 Info:   Configures a generic board or HAT using ESS Sabre ES9023 DAC
 Load:   dtoverlay=simple-es9023-audio,<param>,<param>=<val>

arch/arm/boot/dts/overlays/simple-bclk-64fs-overlay.dts

@@ -0,0 +1,44 @@
+// Always use a 64fs bclk_ratio
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "brcm,bcm2708";
+
+	fragment@0 {
+		target = <&sound>;
+		__overlay__ {
+			// 2ch, 32/24/16bit rule
+			// set bclk_ratio=64
+			hw-params-rule@0 {
+				rule-name = "32/24/16BIT_2CH_BCLK64";
+				priority = <99>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_channels";
+					values = <2>;
+				};
+				match@1 {
+					method = "asoc_generic_hw_params_match_sample_bits";
+					values = <32>, <24>, <16>;
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <64>;
+				};
+			};
+			// default rule
+			// set blck_ratio=0 (Let cpu driver decide bclk_ratio)
+			hw-params-rule@1 {
+				rule-name = "DEFAULT_BCLK0";
+				priority = <0>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_noop";
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <0>;
+				};
+			};
+		};
+	};
+};

arch/arm/boot/dts/overlays/simple-bclk-int-div-40-80-overlay.dts

@@ -0,0 +1,79 @@
+// Definitions of bclk_integer_divisor preference for multiples of 8k rates.
+//  bclk_ratio=40 for S16_LE. bclk_ratio=80 for S24_LE and S32_LE.
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "brcm,bcm2708";
+
+	fragment@0 {
+		target = <&sound>;
+		__overlay__ {
+			// 2ch, 32bit @ 8/16/32/48/64/96kHz rule
+			// set bclk_ratio=80
+			hw-params-rule@0 {
+				rule-name = "x8kHz_32BIT_2CH_BCLK80";
+				priority = <99>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_channels";
+					values = <2>;
+				};
+				match@1 {
+					method = "asoc_generic_hw_params_match_rate_lt";
+					value = <192000>;
+				};
+				match@2 {
+					method = "asoc_generic_hw_params_match_rate_div_by";
+					value = <8000>;
+				};
+				match@3 {
+					method = "asoc_generic_hw_params_match_sample_bits";
+					values = <32>;
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <80>;
+				};
+			};
+			// 2ch, 16bit @ 8/16/32/48/64/96kHz rule
+			// set bclk_ratio=40
+			hw-params-rule@1 {
+				rule-name = "x8kHz_16BIT_2CH_BCLK40";
+				priority = <99>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_channels";
+					values = <2>;
+				};
+				match@1 {
+					method = "asoc_generic_hw_params_match_rate_lt";
+					value = <192000>;
+				};
+				match@2 {
+					method = "asoc_generic_hw_params_match_rate_div_by";
+					value = <8000>;
+				};
+				match@3 {
+					method = "asoc_generic_hw_params_match_sample_bits";
+					values = <16>;
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <40>;
+				};
+			};
+			// default rule
+			// set blck_ratio=0 (Let cpu driver decide bclk_ratio)
+			hw-params-rule@2 {
+				rule-name = "DEFAULT_BCLK0";
+				priority = <0>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_noop";
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <0>;
+				};
+			};
+		};
+	};
+};

arch/arm/boot/dts/overlays/simple-bclk-int-div-50-100-overlay.dts

@@ -0,0 +1,79 @@
+// Definitions of bclk_integer_divisor preference for multiples of 8k rates.
+//  bclk_ratio=50 for S16_LE. bclk_ratio=100 for S24_LE and S32_LE.
+/dts-v1/;
+/plugin/;
+
+/ {
+	compatible = "brcm,bcm2708";
+
+	fragment@0 {
+		target = <&sound>;
+		__overlay__ {
+			// 2ch, 32bit @ 8/16/32/48/64/96kHz rule
+			// set bclk_ratio=100
+			hw-params-rule@0 {
+				rule-name = "x8kHz_32BIT_2CH_BCLK100";
+				priority = <99>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_channels";
+					values = <2>;
+				};
+				match@1 {
+					method = "asoc_generic_hw_params_match_rate_lt";
+					value = <192000>;
+				};
+				match@2 {
+					method = "asoc_generic_hw_params_match_rate_div_by";
+					value = <8000>;
+				};
+				match@3 {
+					method = "asoc_generic_hw_params_match_sample_bits";
+					values = <32>;
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <100>;
+				};
+			};
+			// 2ch, 16bit @ 8/16/32/48/64/96kHz rule
+			// set bclk_ratio=50
+			hw-params-rule@1 {
+				rule-name = "x8kHz_16BIT_2CH_BCLK50";
+				priority = <99>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_channels";
+					values = <2>;
+				};
+				match@1 {
+					method = "asoc_generic_hw_params_match_rate_lt";
+					value = <192000>;
+				};
+				match@2 {
+					method = "asoc_generic_hw_params_match_rate_div_by";
+					value = <8000>;
+				};
+				match@3 {
+					method = "asoc_generic_hw_params_match_sample_bits";
+					values = <16>;
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <50>;
+				};
+			};
+			// default rule
+			// set blck_ratio=0 (Let cpu driver decide bclk_ratio)
+			hw-params-rule@2 {
+				rule-name = "DEFAULT_BCLK0";
+				priority = <0>;
+				match@0 {
+					method = "asoc_generic_hw_params_match_noop";
+				};
+				action@0 {
+					method = "asoc_generic_hw_params_set_fixed_bclk_size";
+					value = <0>;
+				};
+			};
+		};
+	};
+};