/
if_bce.c
7980 lines (6663 loc) · 253 KB
/
if_bce.c
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/*-
* Copyright (c) 2006-2007 Broadcom Corporation
* David Christensen <davidch@broadcom.com>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of Broadcom Corporation nor the name of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written consent.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
*/
/*
* The following controllers are supported by this driver:
* BCM5706C A2, A3
* BCM5706S A2, A3
* BCM5708C B1, B2
* BCM5708S B1, B2
* BCM5709C A1, C0
* BCM5716 C0
*
* The following controllers are not supported by this driver:
* BCM5706C A0, A1
* BCM5706S A0, A1
* BCM5708C A0, B0
* BCM5708S A0, B0
* BCM5709C A0, B0, B1
* BCM5709S A0, A1, B0, B1, B2, C0
*/
#include "opt_bce.h"
#include "opt_polling.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/kernel.h>
#include <sys/interrupt.h>
#include <sys/mbuf.h>
#include <sys/malloc.h>
#include <sys/queue.h>
#ifdef BCE_DEBUG
#include <sys/random.h>
#endif
#include <sys/rman.h>
#include <sys/serialize.h>
#include <sys/socket.h>
#include <sys/sockio.h>
#include <sys/sysctl.h>
#include <net/bpf.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_dl.h>
#include <net/if_media.h>
#include <net/if_types.h>
#include <net/ifq_var.h>
#include <net/vlan/if_vlan_var.h>
#include <net/vlan/if_vlan_ether.h>
#include <dev/netif/mii_layer/mii.h>
#include <dev/netif/mii_layer/miivar.h>
#include <bus/pci/pcireg.h>
#include <bus/pci/pcivar.h>
#include "miibus_if.h"
#include <dev/netif/bce/if_bcereg.h>
#include <dev/netif/bce/if_bcefw.h>
/****************************************************************************/
/* BCE Debug Options */
/****************************************************************************/
#ifdef BCE_DEBUG
static uint32_t bce_debug = BCE_WARN;
/*
* 0 = Never
* 1 = 1 in 2,147,483,648
* 256 = 1 in 8,388,608
* 2048 = 1 in 1,048,576
* 65536 = 1 in 32,768
* 1048576 = 1 in 2,048
* 268435456 = 1 in 8
* 536870912 = 1 in 4
* 1073741824 = 1 in 2
*
* bce_debug_l2fhdr_status_check:
* How often the l2_fhdr frame error check will fail.
*
* bce_debug_unexpected_attention:
* How often the unexpected attention check will fail.
*
* bce_debug_mbuf_allocation_failure:
* How often to simulate an mbuf allocation failure.
*
* bce_debug_dma_map_addr_failure:
* How often to simulate a DMA mapping failure.
*
* bce_debug_bootcode_running_failure:
* How often to simulate a bootcode failure.
*/
static int bce_debug_l2fhdr_status_check = 0;
static int bce_debug_unexpected_attention = 0;
static int bce_debug_mbuf_allocation_failure = 0;
static int bce_debug_dma_map_addr_failure = 0;
static int bce_debug_bootcode_running_failure = 0;
#endif /* BCE_DEBUG */
/****************************************************************************/
/* PCI Device ID Table */
/* */
/* Used by bce_probe() to identify the devices supported by this driver. */
/****************************************************************************/
#define BCE_DEVDESC_MAX 64
static struct bce_type bce_devs[] = {
/* BCM5706C Controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3101,
"HP NC370T Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3106,
"HP NC370i Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x3070,
"HP NC380T PCIe DP Multifunc Gig Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706, HP_VENDORID, 0x1709,
"HP NC371i Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5706 1000Base-T" },
/* BCM5706S controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
"HP NC370F Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5706 1000Base-SX" },
/* BCM5708C controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7037,
"HP NC373T PCIe Multifunction Gig Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7038,
"HP NC373i Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708, HP_VENDORID, 0x7045,
"HP NC374m PCIe Multifunction Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5708 1000Base-T" },
/* BCM5708S controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x1706,
"HP NC373m Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703b,
"HP NC373i Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, HP_VENDORID, 0x703d,
"HP NC373F PCIe Multifunc Giga Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5708S 1000Base-T" },
/* BCM5709C controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7055,
"HP NC382i DP Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709, HP_VENDORID, 0x7059,
"HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5709 1000Base-T" },
/* BCM5709S controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x171d,
"HP NC382m DP 1GbE Multifunction BL-c Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, HP_VENDORID, 0x7056,
"HP NC382i DP Multifunction Gigabit Server Adapter" },
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5709 1000Base-SX" },
/* BCM5716 controllers and OEM boards. */
{ BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
"Broadcom NetXtreme II BCM5716 1000Base-T" },
{ 0, 0, 0, 0, NULL }
};
/****************************************************************************/
/* Supported Flash NVRAM device data. */
/****************************************************************************/
static const struct flash_spec flash_table[] =
{
#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
#define NONBUFFERED_FLAGS (BCE_NV_WREN)
/* Slow EEPROM */
{0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
"EEPROM - slow"},
/* Expansion entry 0001 */
{0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
"Entry 0001"},
/* Saifun SA25F010 (non-buffered flash) */
/* strap, cfg1, & write1 need updates */
{0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
"Non-buffered flash (128kB)"},
/* Saifun SA25F020 (non-buffered flash) */
/* strap, cfg1, & write1 need updates */
{0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
"Non-buffered flash (256kB)"},
/* Expansion entry 0100 */
{0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
"Entry 0100"},
/* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
{0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
"Entry 0101: ST M45PE10 (128kB non-bufferred)"},
/* Entry 0110: ST M45PE20 (non-buffered flash)*/
{0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
"Entry 0110: ST M45PE20 (256kB non-bufferred)"},
/* Saifun SA25F005 (non-buffered flash) */
/* strap, cfg1, & write1 need updates */
{0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
"Non-buffered flash (64kB)"},
/* Fast EEPROM */
{0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
"EEPROM - fast"},
/* Expansion entry 1001 */
{0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
"Entry 1001"},
/* Expansion entry 1010 */
{0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
"Entry 1010"},
/* ATMEL AT45DB011B (buffered flash) */
{0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
"Buffered flash (128kB)"},
/* Expansion entry 1100 */
{0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
"Entry 1100"},
/* Expansion entry 1101 */
{0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
"Entry 1101"},
/* Ateml Expansion entry 1110 */
{0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
"Entry 1110 (Atmel)"},
/* ATMEL AT45DB021B (buffered flash) */
{0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
"Buffered flash (256kB)"},
};
/*
* The BCM5709 controllers transparently handle the
* differences between Atmel 264 byte pages and all
* flash devices which use 256 byte pages, so no
* logical-to-physical mapping is required in the
* driver.
*/
static struct flash_spec flash_5709 = {
.flags = BCE_NV_BUFFERED,
.page_bits = BCM5709_FLASH_PAGE_BITS,
.page_size = BCM5709_FLASH_PAGE_SIZE,
.addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
.total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
.name = "5709/5716 buffered flash (256kB)",
};
/****************************************************************************/
/* DragonFly device entry points. */
/****************************************************************************/
static int bce_probe(device_t);
static int bce_attach(device_t);
static int bce_detach(device_t);
static void bce_shutdown(device_t);
/****************************************************************************/
/* BCE Debug Data Structure Dump Routines */
/****************************************************************************/
#ifdef BCE_DEBUG
static void bce_dump_mbuf(struct bce_softc *, struct mbuf *);
static void bce_dump_tx_mbuf_chain(struct bce_softc *, int, int);
static void bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
static void bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
static void bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
static void bce_dump_l2fhdr(struct bce_softc *, int,
struct l2_fhdr *) __unused;
static void bce_dump_tx_chain(struct bce_softc *, int, int);
static void bce_dump_rx_chain(struct bce_softc *, int, int);
static void bce_dump_status_block(struct bce_softc *);
static void bce_dump_driver_state(struct bce_softc *);
static void bce_dump_stats_block(struct bce_softc *) __unused;
static void bce_dump_hw_state(struct bce_softc *);
static void bce_dump_txp_state(struct bce_softc *);
static void bce_dump_rxp_state(struct bce_softc *) __unused;
static void bce_dump_tpat_state(struct bce_softc *) __unused;
static void bce_freeze_controller(struct bce_softc *) __unused;
static void bce_unfreeze_controller(struct bce_softc *) __unused;
static void bce_breakpoint(struct bce_softc *);
#endif /* BCE_DEBUG */
/****************************************************************************/
/* BCE Register/Memory Access Routines */
/****************************************************************************/
static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
static void bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
static void bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
static uint32_t bce_shmem_rd(struct bce_softc *, u32);
static void bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
static int bce_miibus_read_reg(device_t, int, int);
static int bce_miibus_write_reg(device_t, int, int, int);
static void bce_miibus_statchg(device_t);
/****************************************************************************/
/* BCE NVRAM Access Routines */
/****************************************************************************/
static int bce_acquire_nvram_lock(struct bce_softc *);
static int bce_release_nvram_lock(struct bce_softc *);
static void bce_enable_nvram_access(struct bce_softc *);
static void bce_disable_nvram_access(struct bce_softc *);
static int bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
uint32_t);
static int bce_init_nvram(struct bce_softc *);
static int bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
static int bce_nvram_test(struct bce_softc *);
/****************************************************************************/
/* BCE DMA Allocate/Free Routines */
/****************************************************************************/
static int bce_dma_alloc(struct bce_softc *);
static void bce_dma_free(struct bce_softc *);
static void bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
/****************************************************************************/
/* BCE Firmware Synchronization and Load */
/****************************************************************************/
static int bce_fw_sync(struct bce_softc *, uint32_t);
static void bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
uint32_t, uint32_t);
static void bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
struct fw_info *);
static void bce_start_cpu(struct bce_softc *, struct cpu_reg *);
static void bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
static void bce_start_rxp_cpu(struct bce_softc *);
static void bce_init_rxp_cpu(struct bce_softc *);
static void bce_init_txp_cpu(struct bce_softc *);
static void bce_init_tpat_cpu(struct bce_softc *);
static void bce_init_cp_cpu(struct bce_softc *);
static void bce_init_com_cpu(struct bce_softc *);
static void bce_init_cpus(struct bce_softc *);
static void bce_stop(struct bce_softc *);
static int bce_reset(struct bce_softc *, uint32_t);
static int bce_chipinit(struct bce_softc *);
static int bce_blockinit(struct bce_softc *);
static int bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
uint32_t *, int);
static void bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
static void bce_probe_pci_caps(struct bce_softc *);
static void bce_print_adapter_info(struct bce_softc *);
static void bce_get_media(struct bce_softc *);
static void bce_init_tx_context(struct bce_softc *);
static int bce_init_tx_chain(struct bce_softc *);
static void bce_init_rx_context(struct bce_softc *);
static int bce_init_rx_chain(struct bce_softc *);
static void bce_free_rx_chain(struct bce_softc *);
static void bce_free_tx_chain(struct bce_softc *);
static int bce_encap(struct bce_softc *, struct mbuf **);
static void bce_start(struct ifnet *);
static int bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
static void bce_watchdog(struct ifnet *);
static int bce_ifmedia_upd(struct ifnet *);
static void bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
static void bce_init(void *);
static void bce_mgmt_init(struct bce_softc *);
static int bce_init_ctx(struct bce_softc *);
static void bce_get_mac_addr(struct bce_softc *);
static void bce_set_mac_addr(struct bce_softc *);
static void bce_phy_intr(struct bce_softc *);
static void bce_rx_intr(struct bce_softc *, int);
static void bce_tx_intr(struct bce_softc *);
static void bce_disable_intr(struct bce_softc *);
static void bce_enable_intr(struct bce_softc *, int);
#ifdef DEVICE_POLLING
static void bce_poll(struct ifnet *, enum poll_cmd, int);
#endif
static void bce_intr(void *);
static void bce_set_rx_mode(struct bce_softc *);
static void bce_stats_update(struct bce_softc *);
static void bce_tick(void *);
static void bce_tick_serialized(struct bce_softc *);
static void bce_pulse(void *);
static void bce_add_sysctls(struct bce_softc *);
static void bce_coal_change(struct bce_softc *);
static int bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
static int bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
uint32_t *, uint32_t);
/*
* NOTE:
* Don't set bce_tx_ticks_int/bce_tx_ticks to 1023. Linux's bnx2
* takes 1023 as the TX ticks limit. However, using 1023 will
* cause 5708(B2) to generate extra interrupts (~2000/s) even when
* there is _no_ network activity on the NIC.
*/
static uint32_t bce_tx_bds_int = 255; /* bcm: 20 */
static uint32_t bce_tx_bds = 255; /* bcm: 20 */
static uint32_t bce_tx_ticks_int = 1022; /* bcm: 80 */
static uint32_t bce_tx_ticks = 1022; /* bcm: 80 */
static uint32_t bce_rx_bds_int = 128; /* bcm: 6 */
static uint32_t bce_rx_bds = 128; /* bcm: 6 */
static uint32_t bce_rx_ticks_int = 125; /* bcm: 18 */
static uint32_t bce_rx_ticks = 125; /* bcm: 18 */
static int bce_msi_enable = 1;
TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
/****************************************************************************/
/* DragonFly device dispatch table. */
/****************************************************************************/
static device_method_t bce_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, bce_probe),
DEVMETHOD(device_attach, bce_attach),
DEVMETHOD(device_detach, bce_detach),
DEVMETHOD(device_shutdown, bce_shutdown),
/* bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_driver_added, bus_generic_driver_added),
/* MII interface */
DEVMETHOD(miibus_readreg, bce_miibus_read_reg),
DEVMETHOD(miibus_writereg, bce_miibus_write_reg),
DEVMETHOD(miibus_statchg, bce_miibus_statchg),
{ 0, 0 }
};
static driver_t bce_driver = {
"bce",
bce_methods,
sizeof(struct bce_softc)
};
static devclass_t bce_devclass;
DECLARE_DUMMY_MODULE(if_bce);
MODULE_DEPEND(bce, miibus, 1, 1, 1);
DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
/****************************************************************************/
/* Device probe function. */
/* */
/* Compares the device to the driver's list of supported devices and */
/* reports back to the OS whether this is the right driver for the device. */
/* */
/* Returns: */
/* BUS_PROBE_DEFAULT on success, positive value on failure. */
/****************************************************************************/
static int
bce_probe(device_t dev)
{
struct bce_type *t;
uint16_t vid, did, svid, sdid;
/* Get the data for the device to be probed. */
vid = pci_get_vendor(dev);
did = pci_get_device(dev);
svid = pci_get_subvendor(dev);
sdid = pci_get_subdevice(dev);
/* Look through the list of known devices for a match. */
for (t = bce_devs; t->bce_name != NULL; ++t) {
if (vid == t->bce_vid && did == t->bce_did &&
(svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
(sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
char *descbuf;
descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
/* Print out the device identity. */
ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
t->bce_name,
((revid & 0xf0) >> 4) + 'A', revid & 0xf);
device_set_desc_copy(dev, descbuf);
kfree(descbuf, M_TEMP);
return 0;
}
}
return ENXIO;
}
/****************************************************************************/
/* PCI Capabilities Probe Function. */
/* */
/* Walks the PCI capabiites list for the device to find what features are */
/* supported. */
/* */
/* Returns: */
/* None. */
/****************************************************************************/
static void
bce_print_adapter_info(struct bce_softc *sc)
{
device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
/* Bus info. */
if (sc->bce_flags & BCE_PCIE_FLAG) {
kprintf("Bus (PCIe x%d, ", sc->link_width);
switch (sc->link_speed) {
case 1:
kprintf("2.5Gbps); ");
break;
case 2:
kprintf("5Gbps); ");
break;
default:
kprintf("Unknown link speed); ");
break;
}
} else {
kprintf("Bus (PCI%s, %s, %dMHz); ",
((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
sc->bus_speed_mhz);
}
/* Firmware version and device features. */
kprintf("B/C (%s)", sc->bce_bc_ver);
if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
(sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
kprintf("; Flags(");
if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
kprintf("MFW[%s]", sc->bce_mfw_ver);
if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
kprintf(" 2.5G");
kprintf(")");
}
kprintf("\n");
}
/****************************************************************************/
/* PCI Capabilities Probe Function. */
/* */
/* Walks the PCI capabiites list for the device to find what features are */
/* supported. */
/* */
/* Returns: */
/* None. */
/****************************************************************************/
static void
bce_probe_pci_caps(struct bce_softc *sc)
{
device_t dev = sc->bce_dev;
uint8_t ptr;
if (pci_is_pcix(dev))
sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
ptr = pci_get_pciecap_ptr(dev);
if (ptr) {
uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
sc->link_speed = link_status & 0xf;
sc->link_width = (link_status >> 4) & 0x3f;
sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
sc->bce_flags |= BCE_PCIE_FLAG;
}
}
/****************************************************************************/
/* Device attach function. */
/* */
/* Allocates device resources, performs secondary chip identification, */
/* resets and initializes the hardware, and initializes driver instance */
/* variables. */
/* */
/* Returns: */
/* 0 on success, positive value on failure. */
/****************************************************************************/
static int
bce_attach(device_t dev)
{
struct bce_softc *sc = device_get_softc(dev);
struct ifnet *ifp = &sc->arpcom.ac_if;
uint32_t val;
u_int irq_flags;
int rid, rc = 0, msi_enable;
int i, j;
char env[64];
sc->bce_dev = dev;
if_initname(ifp, device_get_name(dev), device_get_unit(dev));
pci_enable_busmaster(dev);
bce_probe_pci_caps(sc);
/* Allocate PCI memory resources. */
rid = PCIR_BAR(0);
sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE | PCI_RF_DENSE);
if (sc->bce_res_mem == NULL) {
device_printf(dev, "PCI memory allocation failed\n");
return ENXIO;
}
sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
/* Allocate PCI IRQ resources. */
msi_enable = bce_msi_enable;
ksnprintf(env, sizeof(env), "hw.%s.msi.enable",
device_get_nameunit(dev));
kgetenv_int(env, &msi_enable);
sc->bce_irq_rid = 0;
sc->bce_irq_type = BCE_IRQ_TYPE_LEGACY;
irq_flags = RF_SHAREABLE | RF_ACTIVE;
if (msi_enable) {
int cpu = -1;
ksnprintf(env, sizeof(env), "hw.%s.msi.cpu",
device_get_nameunit(dev));
kgetenv_int(env, &cpu);
if (cpu >= ncpus)
cpu = ncpus - 1;
if (pci_alloc_msi(dev, &sc->bce_irq_rid, 1, cpu) == 0) {
irq_flags &= ~RF_SHAREABLE;
sc->bce_irq_type = BCE_IRQ_TYPE_MSI;
}
}
sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
&sc->bce_irq_rid, irq_flags);
if (sc->bce_res_irq == NULL) {
device_printf(dev, "PCI map interrupt failed\n");
rc = ENXIO;
goto fail;
}
/*
* Configure byte swap and enable indirect register access.
* Rely on CPU to do target byte swapping on big endian systems.
* Access to registers outside of PCI configurtion space are not
* valid until this is done.
*/
pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
/* Save ASIC revsion info. */
sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
/* Weed out any non-production controller revisions. */
switch (BCE_CHIP_ID(sc)) {
case BCE_CHIP_ID_5706_A0:
case BCE_CHIP_ID_5706_A1:
case BCE_CHIP_ID_5708_A0:
case BCE_CHIP_ID_5708_B0:
case BCE_CHIP_ID_5709_A0:
case BCE_CHIP_ID_5709_B0:
case BCE_CHIP_ID_5709_B1:
#ifdef foo
/* 5709C B2 seems to work fine */
case BCE_CHIP_ID_5709_B2:
#endif
device_printf(dev, "Unsupported chip id 0x%08x!\n",
BCE_CHIP_ID(sc));
rc = ENODEV;
goto fail;
}
/*
* Find the base address for shared memory access.
* Newer versions of bootcode use a signature and offset
* while older versions use a fixed address.
*/
val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
BCE_SHM_HDR_SIGNATURE_SIG) {
/* Multi-port devices use different offsets in shared memory. */
sc->bce_shmem_base = REG_RD_IND(sc,
BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
} else {
sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
}
DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
/* Fetch the bootcode revision. */
val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
for (i = 0, j = 0; i < 3; i++) {
uint8_t num;
int k, skip0;
num = (uint8_t)(val >> (24 - (i * 8)));
for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
if (num >= k || !skip0 || k == 1) {
sc->bce_bc_ver[j++] = (num / k) + '0';
skip0 = 0;
}
}
if (i != 2)
sc->bce_bc_ver[j++] = '.';
}
/* Check if any management firwmare is running. */
val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
/* Allow time for firmware to enter the running state. */
for (i = 0; i < 30; i++) {
val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
if (val & BCE_CONDITION_MFW_RUN_MASK)
break;
DELAY(10000);
}
}
/* Check the current bootcode state. */
val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
BCE_CONDITION_MFW_RUN_MASK;
if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
val != BCE_CONDITION_MFW_RUN_NONE) {
uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
for (i = 0, j = 0; j < 3; j++) {
val = bce_reg_rd_ind(sc, addr + j * 4);
val = bswap32(val);
memcpy(&sc->bce_mfw_ver[i], &val, 4);
i += 4;
}
}
/* Get PCI bus information (speed and type). */
val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
uint32_t clkreg;
sc->bce_flags |= BCE_PCIX_FLAG;
clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
switch (clkreg) {
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
sc->bus_speed_mhz = 133;
break;
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
sc->bus_speed_mhz = 100;
break;
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
sc->bus_speed_mhz = 66;
break;
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
sc->bus_speed_mhz = 50;
break;
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
sc->bus_speed_mhz = 33;
break;
}
} else {
if (val & BCE_PCICFG_MISC_STATUS_M66EN)
sc->bus_speed_mhz = 66;
else
sc->bus_speed_mhz = 33;
}
if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
sc->bce_flags |= BCE_PCI_32BIT_FLAG;
/* Reset the controller. */
rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
if (rc != 0)
goto fail;
/* Initialize the controller. */
rc = bce_chipinit(sc);
if (rc != 0) {
device_printf(dev, "Controller initialization failed!\n");
goto fail;
}
/* Perform NVRAM test. */
rc = bce_nvram_test(sc);
if (rc != 0) {
device_printf(dev, "NVRAM test failed!\n");
goto fail;
}
/* Fetch the permanent Ethernet MAC address. */
bce_get_mac_addr(sc);
/*
* Trip points control how many BDs
* should be ready before generating an
* interrupt while ticks control how long
* a BD can sit in the chain before
* generating an interrupt. Set the default
* values for the RX and TX rings.
*/
#ifdef BCE_DRBUG
/* Force more frequent interrupts. */
sc->bce_tx_quick_cons_trip_int = 1;
sc->bce_tx_quick_cons_trip = 1;
sc->bce_tx_ticks_int = 0;
sc->bce_tx_ticks = 0;
sc->bce_rx_quick_cons_trip_int = 1;
sc->bce_rx_quick_cons_trip = 1;
sc->bce_rx_ticks_int = 0;
sc->bce_rx_ticks = 0;
#else
sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
sc->bce_tx_quick_cons_trip = bce_tx_bds;
sc->bce_tx_ticks_int = bce_tx_ticks_int;
sc->bce_tx_ticks = bce_tx_ticks;
sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
sc->bce_rx_quick_cons_trip = bce_rx_bds;
sc->bce_rx_ticks_int = bce_rx_ticks_int;
sc->bce_rx_ticks = bce_rx_ticks;
#endif
/* Update statistics once every second. */
sc->bce_stats_ticks = 1000000 & 0xffff00;
/* Find the media type for the adapter. */
bce_get_media(sc);
/* Allocate DMA memory resources. */
rc = bce_dma_alloc(sc);
if (rc != 0) {
device_printf(dev, "DMA resource allocation failed!\n");
goto fail;
}
/* Initialize the ifnet interface. */
ifp->if_softc = sc;
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
ifp->if_ioctl = bce_ioctl;
ifp->if_start = bce_start;
ifp->if_init = bce_init;
ifp->if_watchdog = bce_watchdog;
#ifdef DEVICE_POLLING
ifp->if_poll = bce_poll;
#endif
ifp->if_mtu = ETHERMTU;
ifp->if_hwassist = BCE_IF_HWASSIST;
ifp->if_capabilities = BCE_IF_CAPABILITIES;
ifp->if_capenable = ifp->if_capabilities;
ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD);
ifq_set_ready(&ifp->if_snd);
if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
ifp->if_baudrate = IF_Gbps(2.5);
else
ifp->if_baudrate = IF_Gbps(1);
/* Assume a standard 1500 byte MTU size for mbuf allocations. */
sc->mbuf_alloc_size = MCLBYTES;
/* Look for our PHY. */
rc = mii_phy_probe(dev, &sc->bce_miibus,
bce_ifmedia_upd, bce_ifmedia_sts);
if (rc != 0) {
device_printf(dev, "PHY probe failed!\n");
goto fail;
}
/* Attach to the Ethernet interface list. */
ether_ifattach(ifp, sc->eaddr, NULL);
callout_init_mp(&sc->bce_tick_callout);
callout_init_mp(&sc->bce_pulse_callout);
/* Hookup IRQ last. */
rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, bce_intr, sc,
&sc->bce_intrhand, ifp->if_serializer);
if (rc != 0) {
device_printf(dev, "Failed to setup IRQ!\n");
ether_ifdetach(ifp);
goto fail;
}
ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->bce_res_irq));
KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
/* Print some important debugging info. */
DBRUN(BCE_INFO, bce_dump_driver_state(sc));
/* Add the supported sysctls to the kernel. */
bce_add_sysctls(sc);
/*
* The chip reset earlier notified the bootcode that
* a driver is present. We now need to start our pulse
* routine so that the bootcode is reminded that we're
* still running.
*/
bce_pulse(sc);
/* Get the firmware running so IPMI still works */
bce_mgmt_init(sc);
if (bootverbose)
bce_print_adapter_info(sc);