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i#6778: Gracefully handle too few drcachesim cpus
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Adds a check with an error message for too few simulated drcachesim
cpus with a core-sharded-on-disk trace.

Adds a unit test which crashes without the fix.

Also tested manually:
Before:
  $ bin64/drrun -t drcachesim -indir ../src/clients/drcachesim/tests/drmemtrace.threadsig-core-sharded.x64.tracedir/ -cores 3
  Segmentation fault
After:
  $ bin64/drrun -t drcachesim -indir ../src/clients/drcachesim/tests/drmemtrace.threadsig-core-sharded.x64.tracedir/ -cores 3
  ERROR: failed to run analyzer: Too-small core count 3 for trace core #3

Fixes #6778
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derekbruening committed Apr 18, 2024
1 parent eb79973 commit 0cb5ea9
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5 changes: 5 additions & 0 deletions clients/drcachesim/simulator/cache_simulator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -469,6 +469,11 @@ cache_simulator_t::process_memref(const memref_t &memref)
}
} else
core_index = core_for_thread(memref.data.tid);
if (core_index >= static_cast<int>(knobs_.num_cores)) {
error_string_ = "Too-small core count " + std::to_string(knobs_.num_cores) +
" for trace core #" + std::to_string(core_index);
return false;
}

// To support swapping to physical addresses without modifying the passed-in
// memref (which is also passed to other tools run at the same time) we use
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17 changes: 17 additions & 0 deletions clients/drcachesim/tests/drcachesim_unit_tests.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -814,6 +814,23 @@ Core #1 \(traced CPU\(s\): #567800\)
)DELIM")));
#endif
}
{
// Test graceful handling of too-few cpus.
cache_simulator_knobs_t knobs = make_test_knobs();
knobs.num_cores = 2;
cache_simulator_t sim(knobs);
default_memtrace_stream_t stream;
sim.initialize_stream(&stream);
std::string error = sim.initialize_shard_type(SHARD_BY_CORE);
assert(error.empty());
memref_t ref = make_memref(42);
stream.set_shard_index(2); // Too large for knobs.num_cores.
stream.set_output_cpuid(1);
bool res = sim.process_memref(ref);
// We should see graceful failure and not a crash.
assert(!res);
assert(!sim.get_error_string().empty());
}
}

int
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