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i#3044 AArch64 SVE codec: PRF* scalar index
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This patch adds the appropriate macros, tests and codec entries
to encode the following variants:
PRFB    <prfop>, <Pg>, [<Xn|SP>, <Xm>]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]

Issue: #3044
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@jackgallagher-arm
jackgallagher-arm committed Apr 26, 2023
1 parent 4a4ff42 commit 242f013
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Showing 6 changed files with 164 additions and 0 deletions.
19 changes: 19 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7004,6 +7004,25 @@ encode_opnd_svemem_vec_d_imm5(uint enc, int opcode, byte *pc, opnd_t opnd,
return encode_svemem_vec_imm5(enc, DOUBLE_REG, op_is_prefetch(opcode), opnd, enc_out);
}

/* sveprf_gpr_shf: SVE memory address [<Xn|SP>, <Xm>, LSL #x] for prefetch operations */

static inline bool
decode_opnd_sveprf_gpr_shf(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
const uint shift_amount = BITS(enc, 24, 23);

return svemem_gprs_per_element_decode(OPSZ_0, shift_amount, enc, opcode, pc, opnd);
}

static inline bool
encode_opnd_sveprf_gpr_shf(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
const uint shift_amount = BITS(enc, 24, 23);

return svemem_gprs_per_element_encode(OPSZ_0, shift_amount, enc, opcode, pc, opnd,
enc_out);
}

/* SVE memory address (64-bit offset) [<Xn|SP>, <Zm>.D{, <mod>}] */
static inline bool
decode_opnd_svemem_gpr_vec64(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
Expand Down
4 changes: 4 additions & 0 deletions core/ir/aarch64/codec_sve.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -558,24 +558,28 @@
11000100011xxxxx100xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo sveprf_gpr_vec64
110001000x1xxxxx000xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo sveprf_gpr_vec32
100001000x1xxxxx000xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo sveprf_gpr_vec32
10000100000xxxxx110xxxxxxxx0xxxx n 963 SVE prfb : prfop4 p10_lo sveprf_gpr_shf
1000010111xxxxxx011xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo svemem_gpr_simm6_vl
10000101100xxxxx111xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo svemem_vec_s_imm5
11000101100xxxxx111xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo svemem_vec_d_imm5
11000100011xxxxx111xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo sveprf_gpr_vec64
110001000x1xxxxx011xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo sveprf_gpr_vec32
100001000x1xxxxx011xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo sveprf_gpr_vec32
10000101100xxxxx110xxxxxxxx0xxxx n 964 SVE prfd : prfop4 p10_lo sveprf_gpr_shf
1000010111xxxxxx001xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo svemem_gpr_simm6_vl
10000100100xxxxx111xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo svemem_vec_s_imm5
11000100100xxxxx111xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo svemem_vec_d_imm5
11000100011xxxxx101xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo sveprf_gpr_vec64
110001000x1xxxxx001xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo sveprf_gpr_vec32
100001000x1xxxxx001xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo sveprf_gpr_vec32
10000100100xxxxx110xxxxxxxx0xxxx n 965 SVE prfh : prfop4 p10_lo sveprf_gpr_shf
1000010111xxxxxx010xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo svemem_gpr_simm6_vl
10000101000xxxxx111xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo svemem_vec_s_imm5
11000101000xxxxx111xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo svemem_vec_d_imm5
11000100011xxxxx110xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo sveprf_gpr_vec64
110001000x1xxxxx010xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo sveprf_gpr_vec32
100001000x1xxxxx010xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo sveprf_gpr_vec32
10000101000xxxxx110xxxxxxxx0xxxx n 966 SVE prfw : prfop4 p10_lo sveprf_gpr_shf
001001010101000011xxxx0xxxx00000 w 786 SVE ptest : p10 p_b_5
00100101xx011000111000xxxxx0xxxx n 897 SVE ptrue p_size_bhsd_0 : pred_constr
00100101xx011001111000xxxxx0xxxx w 898 SVE ptrues p_size_bhsd_0 : pred_constr
Expand Down
16 changes: 16 additions & 0 deletions core/ir/aarch64/instr_create_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11824,6 +11824,7 @@
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend>]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend>]
* PRFB <prfop>, <Pg>, [<Xn|SP>, <Xm>]
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param prfop The prefetch operation.
Expand All @@ -11847,6 +11848,9 @@
* For the [\<Xn|SP\>, \<Zm\>.S, \<extend\>] variant:
* opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend,
* 0, 0, OPSZ_0, 0)
* For the [\<Xn|SP\>, \<Xm\>] variant:
* opnd_create_base_disp_shift_aarch64(Xn, Xm,
* DR_EXTEND_UXTX, false, 0, 0, OPSZ_0, 0)
*/
#define INSTR_CREATE_prfb_sve_pred(dc, prfop, Pg, Rn) \
instr_create_0dst_3src(dc, OP_prfb, prfop, Pg, Rn)
Expand All @@ -11862,6 +11866,7 @@
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #3]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #3]
* PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param prfop The prefetch operation.
Expand All @@ -11885,6 +11890,9 @@
* For the [\<Xn|SP\>, \<Zm\>.S, \<extend\>] variant:
* opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend,
* true, 0, OPSZ_0, 3)
* For the [\<Xn|SP\>, \<Xm\>] variant:
* opnd_create_base_disp_shift_aarch64(Xn, Xm,
* DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 3)
*/
#define INSTR_CREATE_prfd_sve_pred(dc, prfop, Pg, Rn) \
instr_create_0dst_3src(dc, OP_prfd, prfop, Pg, Rn)
Expand All @@ -11900,6 +11908,7 @@
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #1]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #1]
* PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param prfop The prefetch operation.
Expand All @@ -11923,6 +11932,9 @@
* For the [\<Xn|SP\>, \<Zm\>.S, \<extend\>] variant:
* opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend,
* true, 0, OPSZ_0, 1)
* For the [\<Xn|SP\>, \<Xm\>] variant:
* opnd_create_base_disp_shift_aarch64(Xn, Xm,
* DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 1)
*/
#define INSTR_CREATE_prfh_sve_pred(dc, prfop, Pg, Rn) \
instr_create_0dst_3src(dc, OP_prfh, prfop, Pg, Rn)
Expand All @@ -11938,6 +11950,7 @@
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <extend> #2]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <extend> #2]
* PRFW <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param prfop The prefetch operation.
Expand All @@ -11961,6 +11974,9 @@
* For the [\<Xn|SP\>, \<Zm\>.S, \<extend\>] variant:
* opnd_create_vector_base_disp_aarch64(Xn, Zm, OPSZ_4, extend,
* true, 0, OPSZ_0, 2)
* For the [\<Xn|SP\>, \<Xm\>, LSL #2] variant:
* opnd_create_base_disp_shift_aarch64(Xn, Xm,
* DR_EXTEND_UXTX, true, 0, 0, OPSZ_0, 2)
*/
#define INSTR_CREATE_prfw_sve_pred(dc, prfop, Pg, Rn) \
instr_create_0dst_3src(dc, OP_prfw, prfop, Pg, Rn)
Expand Down
1 change: 1 addition & 0 deletions core/ir/aarch64/opnd_defs.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -320,6 +320,7 @@
--------xx-xxxxx---------------- imm2_tsz_index # Index encoded in imm2:tsz
-------??--xxxxx------xxxxx----- svemem_vec_s_imm5 # SVE memory address [<Zn>.S{, #<imm>}]
-------??--xxxxx------xxxxx----- svemem_vec_d_imm5 # SVE memory address [<Zn>.D{, #<imm>}]
-------??--xxxxx------xxxxx----- sveprf_gpr_shf # SVE memory address [<Xn|SP>, <Xm>, LSL #x] for prefetch operations
-------??-?xxxxx------xxxxx----- svemem_gpr_vec64 # SVE memory address (64-bit offset) [<Xn|SP>, <Zm>.D{, <mod>}]
-------????-xxxx------xxxxx----- svemem_gpr_simm4_vl_1reg # SVE memory operand [<Xn|SP>{, #<imm>, MUL VL}]
# 1 src/dest register
Expand Down
72 changes: 72 additions & 0 deletions suite/tests/api/dis-a64-sve.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -16852,6 +16852,24 @@ a507ffff : ldnt1w z31.s, p7/Z, [sp, #7, MUL VL] : ldnt1w +0x07(%sp)[32byte]
25d9c5cd : pnext p13.d, p14, p13.d : pnext %p14 %p13.d -> %p13.d
25d9c5ef : pnext p15.d, p15, p15.d : pnext %p15 %p15.d -> %p15.d

# PRFB <prfop>, <Pg>, [<Xn|SP>, <Xm>] (PRFB-I.P.BR-S)
8400c000 : prfb PLDL1KEEP, p0, [x0, x0] : prfb $0x00 %p0 (%x0,%x0)
8405c481 : prfb PLDL1STRM, p1, [x4, x5] : prfb $0x01 %p1 (%x4,%x5)
8407c8c2 : prfb PLDL2KEEP, p2, [x6, x7] : prfb $0x02 %p2 (%x6,%x7)
8409c903 : prfb PLDL2STRM, p2, [x8, x9] : prfb $0x03 %p2 (%x8,%x9)
840bcd44 : prfb PLDL3KEEP, p3, [x10, x11] : prfb $0x04 %p3 (%x10,%x11)
840ccd65 : prfb PLDL3STRM, p3, [x11, x12] : prfb $0x05 %p3 (%x11,%x12)
840ed1a6 : prfb 6, p4, [x13, x14] : prfb $0x06 %p4 (%x13,%x14)
8410d1e7 : prfb 7, p4, [x15, x16] : prfb $0x07 %p4 (%x15,%x16)
8412d628 : prfb PSTL1KEEP, p5, [x17, x18] : prfb $0x08 %p5 (%x17,%x18)
8414d669 : prfb PSTL1STRM, p5, [x19, x20] : prfb $0x09 %p5 (%x19,%x20)
8416d6aa : prfb PSTL2KEEP, p5, [x21, x22] : prfb $0x0a %p5 (%x21,%x22)
8418daeb : prfb PSTL2STRM, p6, [x23, x24] : prfb $0x0b %p6 (%x23,%x24)
8419db0c : prfb PSTL3KEEP, p6, [x24, x25] : prfb $0x0c %p6 (%x24,%x25)
841bdf4d : prfb PSTL3STRM, p7, [x26, x27] : prfb $0x0d %p7 (%x26,%x27)
841ddf8e : prfb 14, p7, [x28, x29] : prfb $0x0e %p7 (%x28,%x29)
841edfef : prfb 15, p7, [sp, x30] : prfb $0x0f %p7 (%sp,%x30)

# PRFB <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (PRFB-I.P.AI-S)
8400e000 : prfb PLDL1KEEP, p0, [z0.s, #0] : prfb $0x00 %p0 (%z0.s)
8402e481 : prfb PLDL1STRM, p1, [z4.s, #2] : prfb $0x01 %p1 +0x02(%z4.s)
Expand Down Expand Up @@ -17026,6 +17044,24 @@ c47f9fef : prfb 15, p7, [sp, z31.d] : prfb $0x0f %p7 (%sp,%z3
847e7f8e : prfd 14, p7, [x28, z30.s, SXTW #3] : prfd $0x0e %p7 (%x28,%z30.s,sxtw #3)
847f7fef : prfd 15, p7, [sp, z31.s, SXTW #3] : prfd $0x0f %p7 (%sp,%z31.s,sxtw #3)

# PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3] (PRFD-I.P.BR-S)
8580c000 : prfd PLDL1KEEP, p0, [x0, x0, LSL #3] : prfd $0x00 %p0 (%x0,%x0,lsl #3)
8585c481 : prfd PLDL1STRM, p1, [x4, x5, LSL #3] : prfd $0x01 %p1 (%x4,%x5,lsl #3)
8587c8c2 : prfd PLDL2KEEP, p2, [x6, x7, LSL #3] : prfd $0x02 %p2 (%x6,%x7,lsl #3)
8589c903 : prfd PLDL2STRM, p2, [x8, x9, LSL #3] : prfd $0x03 %p2 (%x8,%x9,lsl #3)
858bcd44 : prfd PLDL3KEEP, p3, [x10, x11, LSL #3] : prfd $0x04 %p3 (%x10,%x11,lsl #3)
858ccd65 : prfd PLDL3STRM, p3, [x11, x12, LSL #3] : prfd $0x05 %p3 (%x11,%x12,lsl #3)
858ed1a6 : prfd 6, p4, [x13, x14, LSL #3] : prfd $0x06 %p4 (%x13,%x14,lsl #3)
8590d1e7 : prfd 7, p4, [x15, x16, LSL #3] : prfd $0x07 %p4 (%x15,%x16,lsl #3)
8592d628 : prfd PSTL1KEEP, p5, [x17, x18, LSL #3] : prfd $0x08 %p5 (%x17,%x18,lsl #3)
8594d669 : prfd PSTL1STRM, p5, [x19, x20, LSL #3] : prfd $0x09 %p5 (%x19,%x20,lsl #3)
8596d6aa : prfd PSTL2KEEP, p5, [x21, x22, LSL #3] : prfd $0x0a %p5 (%x21,%x22,lsl #3)
8598daeb : prfd PSTL2STRM, p6, [x23, x24, LSL #3] : prfd $0x0b %p6 (%x23,%x24,lsl #3)
8599db0c : prfd PSTL3KEEP, p6, [x24, x25, LSL #3] : prfd $0x0c %p6 (%x24,%x25,lsl #3)
859bdf4d : prfd PSTL3STRM, p7, [x26, x27, LSL #3] : prfd $0x0d %p7 (%x26,%x27,lsl #3)
859ddf8e : prfd 14, p7, [x28, x29, LSL #3] : prfd $0x0e %p7 (%x28,%x29,lsl #3)
859edfef : prfd 15, p7, [sp, x30, LSL #3] : prfd $0x0f %p7 (%sp,%x30,lsl #3)

# PRFD <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (PRFD-I.P.AI-S)
8580e000 : prfd PLDL1KEEP, p0, [z0.s, #0] : prfd $0x00 %p0 (%z0.s)
8582e481 : prfd PLDL1STRM, p1, [z4.s, #16] : prfd $0x01 %p1 +0x10(%z4.s)
Expand Down Expand Up @@ -17166,6 +17202,24 @@ c59fffef : prfd 15, p7, [z31.d, #248] : prfd $0x0f %p7 +0xf8(%z
847e3f8e : prfh 14, p7, [x28, z30.s, SXTW #1] : prfh $0x0e %p7 (%x28,%z30.s,sxtw #1)
847f3fef : prfh 15, p7, [sp, z31.s, SXTW #1] : prfh $0x0f %p7 (%sp,%z31.s,sxtw #1)

# PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1] (PRFH-I.P.BR-S)
8480c000 : prfh PLDL1KEEP, p0, [x0, x0, LSL #1] : prfh $0x00 %p0 (%x0,%x0,lsl #1)
8485c481 : prfh PLDL1STRM, p1, [x4, x5, LSL #1] : prfh $0x01 %p1 (%x4,%x5,lsl #1)
8487c8c2 : prfh PLDL2KEEP, p2, [x6, x7, LSL #1] : prfh $0x02 %p2 (%x6,%x7,lsl #1)
8489c903 : prfh PLDL2STRM, p2, [x8, x9, LSL #1] : prfh $0x03 %p2 (%x8,%x9,lsl #1)
848bcd44 : prfh PLDL3KEEP, p3, [x10, x11, LSL #1] : prfh $0x04 %p3 (%x10,%x11,lsl #1)
848ccd65 : prfh PLDL3STRM, p3, [x11, x12, LSL #1] : prfh $0x05 %p3 (%x11,%x12,lsl #1)
848ed1a6 : prfh 6, p4, [x13, x14, LSL #1] : prfh $0x06 %p4 (%x13,%x14,lsl #1)
8490d1e7 : prfh 7, p4, [x15, x16, LSL #1] : prfh $0x07 %p4 (%x15,%x16,lsl #1)
8492d628 : prfh PSTL1KEEP, p5, [x17, x18, LSL #1] : prfh $0x08 %p5 (%x17,%x18,lsl #1)
8494d669 : prfh PSTL1STRM, p5, [x19, x20, LSL #1] : prfh $0x09 %p5 (%x19,%x20,lsl #1)
8496d6aa : prfh PSTL2KEEP, p5, [x21, x22, LSL #1] : prfh $0x0a %p5 (%x21,%x22,lsl #1)
8498daeb : prfh PSTL2STRM, p6, [x23, x24, LSL #1] : prfh $0x0b %p6 (%x23,%x24,lsl #1)
8499db0c : prfh PSTL3KEEP, p6, [x24, x25, LSL #1] : prfh $0x0c %p6 (%x24,%x25,lsl #1)
849bdf4d : prfh PSTL3STRM, p7, [x26, x27, LSL #1] : prfh $0x0d %p7 (%x26,%x27,lsl #1)
849ddf8e : prfh 14, p7, [x28, x29, LSL #1] : prfh $0x0e %p7 (%x28,%x29,lsl #1)
849edfef : prfh 15, p7, [sp, x30, LSL #1] : prfh $0x0f %p7 (%sp,%x30,lsl #1)

# PRFH <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (PRFH-I.P.AI-S)
8480e000 : prfh PLDL1KEEP, p0, [z0.s, #0] : prfh $0x00 %p0 (%z0.s)
8482e481 : prfh PLDL1STRM, p1, [z4.s, #4] : prfh $0x01 %p1 +0x04(%z4.s)
Expand Down Expand Up @@ -17306,6 +17360,24 @@ c49fffef : prfh 15, p7, [z31.d, #62] : prfh $0x0f %p7 +0x3e(%z
847e5f8e : prfw 14, p7, [x28, z30.s, SXTW #2] : prfw $0x0e %p7 (%x28,%z30.s,sxtw #2)
847f5fef : prfw 15, p7, [sp, z31.s, SXTW #2] : prfw $0x0f %p7 (%sp,%z31.s,sxtw #2)

# PRFW <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2] (PRFW-I.P.BR-S)
8500c000 : prfw PLDL1KEEP, p0, [x0, x0, LSL #2] : prfw $0x00 %p0 (%x0,%x0,lsl #2)
8505c481 : prfw PLDL1STRM, p1, [x4, x5, LSL #2] : prfw $0x01 %p1 (%x4,%x5,lsl #2)
8507c8c2 : prfw PLDL2KEEP, p2, [x6, x7, LSL #2] : prfw $0x02 %p2 (%x6,%x7,lsl #2)
8509c903 : prfw PLDL2STRM, p2, [x8, x9, LSL #2] : prfw $0x03 %p2 (%x8,%x9,lsl #2)
850bcd44 : prfw PLDL3KEEP, p3, [x10, x11, LSL #2] : prfw $0x04 %p3 (%x10,%x11,lsl #2)
850ccd65 : prfw PLDL3STRM, p3, [x11, x12, LSL #2] : prfw $0x05 %p3 (%x11,%x12,lsl #2)
850ed1a6 : prfw 6, p4, [x13, x14, LSL #2] : prfw $0x06 %p4 (%x13,%x14,lsl #2)
8510d1e7 : prfw 7, p4, [x15, x16, LSL #2] : prfw $0x07 %p4 (%x15,%x16,lsl #2)
8512d628 : prfw PSTL1KEEP, p5, [x17, x18, LSL #2] : prfw $0x08 %p5 (%x17,%x18,lsl #2)
8514d669 : prfw PSTL1STRM, p5, [x19, x20, LSL #2] : prfw $0x09 %p5 (%x19,%x20,lsl #2)
8516d6aa : prfw PSTL2KEEP, p5, [x21, x22, LSL #2] : prfw $0x0a %p5 (%x21,%x22,lsl #2)
8518daeb : prfw PSTL2STRM, p6, [x23, x24, LSL #2] : prfw $0x0b %p6 (%x23,%x24,lsl #2)
8519db0c : prfw PSTL3KEEP, p6, [x24, x25, LSL #2] : prfw $0x0c %p6 (%x24,%x25,lsl #2)
851bdf4d : prfw PSTL3STRM, p7, [x26, x27, LSL #2] : prfw $0x0d %p7 (%x26,%x27,lsl #2)
851ddf8e : prfw 14, p7, [x28, x29, LSL #2] : prfw $0x0e %p7 (%x28,%x29,lsl #2)
851edfef : prfw 15, p7, [sp, x30, LSL #2] : prfw $0x0f %p7 (%sp,%x30,lsl #2)

# PRFW <prfop>, <Pg>, [<Zn>.S{, #<imm>}] (PRFW-I.P.AI-S)
8500e000 : prfw PLDL1KEEP, p0, [z0.s, #0] : prfw $0x00 %p0 (%z0.s)
8502e481 : prfw PLDL1STRM, p1, [z4.s, #8] : prfw $0x01 %p1 +0x08(%z4.s)
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52 changes: 52 additions & 0 deletions suite/tests/api/ir_aarch64_sve.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16353,6 +16353,19 @@ TEST_INSTR(prfb_sve_pred)
opnd_create_vector_base_disp_aarch64(
Xn_six_offset_2_sp[i], Zn_six_offset_3[i], OPSZ_4, DR_EXTEND_SXTW,
false, 0, 0, OPSZ_0, 0));

/* Testing PRFB <prfop>, <Pg>, [<Xn|SP>, <Xm>] */
const char *const expected_5_0[6] = {
"prfb $0x00 %p0 (%x0,%x0)", "prfb $0x02 %p2 (%x7,%x8)",
"prfb $0x05 %p3 (%x12,%x13)", "prfb $0x08 %p5 (%x17,%x18)",
"prfb $0x0a %p6 (%x22,%x23)", "prfb $0x0f %p7 (%sp,%x30)",
};
TEST_LOOP(prfb, prfb_sve_pred, 6, expected_5_0[i],
opnd_create_immed_uint(prfop[i], OPSZ_4b),
opnd_create_reg(Pn_half_six_offset_0[i]),
opnd_create_base_disp_shift_aarch64(Xn_six_offset_2_sp[i],
Xn_six_offset_3[i], DR_EXTEND_UXTX,
false, 0, 0, OPSZ_0, 0));
}

TEST_INSTR(prfd_sve_pred)
Expand Down Expand Up @@ -16473,6 +16486,19 @@ TEST_INSTR(prfd_sve_pred)
opnd_create_vector_base_disp_aarch64(
Xn_six_offset_2_sp[i], Zn_six_offset_3[i], OPSZ_4, DR_EXTEND_SXTW, true,
0, 0, OPSZ_0, 3));

/* Testing PRFD <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3] */
const char *const expected_5_0[6] = {
"prfd $0x00 %p0 (%x0,%x0,lsl #3)", "prfd $0x02 %p2 (%x7,%x8,lsl #3)",
"prfd $0x05 %p3 (%x12,%x13,lsl #3)", "prfd $0x08 %p5 (%x17,%x18,lsl #3)",
"prfd $0x0a %p6 (%x22,%x23,lsl #3)", "prfd $0x0f %p7 (%sp,%x30,lsl #3)",
};
TEST_LOOP(prfd, prfd_sve_pred, 6, expected_5_0[i],
opnd_create_immed_uint(prfop[i], OPSZ_4b),
opnd_create_reg(Pn_half_six_offset_0[i]),
opnd_create_base_disp_shift_aarch64(Xn_six_offset_2_sp[i],
Xn_six_offset_3[i], DR_EXTEND_UXTX,
true, 0, 0, OPSZ_0, 3));
}

TEST_INSTR(prfh_sve_pred)
Expand Down Expand Up @@ -16594,6 +16620,19 @@ TEST_INSTR(prfh_sve_pred)
opnd_create_vector_base_disp_aarch64(
Xn_six_offset_2_sp[i], Zn_six_offset_3[i], OPSZ_4, DR_EXTEND_SXTW, true,
0, 0, OPSZ_0, 1));

/* Testing PRFH <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1] */
const char *const expected_5_0[6] = {
"prfh $0x00 %p0 (%x0,%x0,lsl #1)", "prfh $0x02 %p2 (%x7,%x8,lsl #1)",
"prfh $0x05 %p3 (%x12,%x13,lsl #1)", "prfh $0x08 %p5 (%x17,%x18,lsl #1)",
"prfh $0x0a %p6 (%x22,%x23,lsl #1)", "prfh $0x0f %p7 (%sp,%x30,lsl #1)",
};
TEST_LOOP(prfh, prfh_sve_pred, 6, expected_5_0[i],
opnd_create_immed_uint(prfop[i], OPSZ_4b),
opnd_create_reg(Pn_half_six_offset_0[i]),
opnd_create_base_disp_shift_aarch64(Xn_six_offset_2_sp[i],
Xn_six_offset_3[i], DR_EXTEND_UXTX,
true, 0, 0, OPSZ_0, 1));
}

TEST_INSTR(prfw_sve_pred)
Expand Down Expand Up @@ -16715,6 +16754,19 @@ TEST_INSTR(prfw_sve_pred)
opnd_create_vector_base_disp_aarch64(
Xn_six_offset_2_sp[i], Zn_six_offset_3[i], OPSZ_4, DR_EXTEND_SXTW, true,
0, 0, OPSZ_0, 2));

/* Testing PRFW <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2] */
const char *const expected_5_0[6] = {
"prfw $0x00 %p0 (%x0,%x0,lsl #2)", "prfw $0x02 %p2 (%x7,%x8,lsl #2)",
"prfw $0x05 %p3 (%x12,%x13,lsl #2)", "prfw $0x08 %p5 (%x17,%x18,lsl #2)",
"prfw $0x0a %p6 (%x22,%x23,lsl #2)", "prfw $0x0f %p7 (%sp,%x30,lsl #2)",
};
TEST_LOOP(prfw, prfw_sve_pred, 6, expected_5_0[i],
opnd_create_immed_uint(prfop[i], OPSZ_4b),
opnd_create_reg(Pn_half_six_offset_0[i]),
opnd_create_base_disp_shift_aarch64(Xn_six_offset_2_sp[i],
Xn_six_offset_3[i], DR_EXTEND_UXTX,
true, 0, 0, OPSZ_0, 2));
}

TEST_INSTR(adr_sve)
Expand Down

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