i#5365: Add AArch64 SVE support to the core (part 1) #5835

AssadHashmi · 2023-01-24T18:44:50Z

This patch adds Arm AArch64 Scalable Vector Extension (SVE) support to
the core including related changes to the codec, IR and relevant clients.

SVE and SVE2 are major extensions to Arm's 64 bit architecture.
Developers and users should reference the relevant documentation at
developer.arm.com, (currently
https://developer.arm.com/Architectures/Scalable%20Vector%20Extensions).

The architecture allows hardware implementations to support vector
lengths from 128 to 2048 bits. This patch supports up to 512 bits due
to DynamoRIO's stack size limitation. There is currently no stock SVE
hardware with vector lengths greater than 512 bits. The vector length
is determined by get_processor_specific_info() at runtime on startup
and is available by calling proc_get_vector_length(). For Z registers,
reg_get_size() will return the vector size implemented by the hardware
rather than OPSZ_SCALABLE.

There will be follow up patches for:

SVE scatter/gather emulation
Full SVE signal context support
Complete SVE support in sample clients and drcachesim tracer.

Issues: #5365, #3044

This patch adds Arm's Scalable Vector Extension vector length support. The vector length is determined at runtime on startup in get_processor_specific_info() and available using proc_get_vector_length(). Cleancall, machine and signal context code have been updated to handle SVE registers as have API functions like reg_get_size() which will return the hardware's vector size rather than OPSZ_SCALABLE. The SVE specification allows for a maximum vector length of 2048 bits. We currently support 512 bits maximum due to DR's stack size limitation. There is currently no stock SVE hardware with vector lengths greater than 512 bits. There will be follow on patches to add: - Predicate registers. - Handling of First Fault Register (FFR). - Targetted SVE tests. Issue: #5365, #3044

AssadHashmi · 2023-01-24T19:30:23Z

Hi @derekbruening and @abhinav92003, this PR is partially complete. I would really appreciate help/advice on the gaps and remaining work please? Also, I'd like some confidence that the current changes are not way off the mark and I've not missed anything significant. The patch has been tested on Graviton 3. Testing on A64FX is pending.

Below are the issues I know of. I have put TODO i#5365 comments in places where I think changes need to be made, including for these:

client.signal test fail
The change in get_clone_record() to handle larger dr_simd_t on the stack works for the basic clone tests but not when cloning and signalling. AFAICT the code_api|client.signal test fails on thread creation. There are two ways of creating threads AFAICT: new_thread_setup() which seems to work with the larger stack and client_thread_run() which doesn't. Possibly something to do with the former using dr_clone_args's stack spec passed in rather than creating it in create_clone_record()? See comments in core/unix/signal.c.
Signal context save/restore
Is this a case of copying the relevant data structs and macros from system headers and updating save/restore code for SVE registers? See comments in core/unix/include/sigcontext.h.

derekbruening · 2023-01-24T23:14:17Z

Signal context save/restore
Is this a case of copying the relevant data structs and macros from system headers and updating save/restore code for SVE registers? See comments in core/unix/include/sigcontext.h.

Yes, we need our frame structs to match the kernel's.

core/unix/signal.c

core/arch/aarch64/proc.c

core/arch/aarchxx/mangle.c

core/ir/aarch64/codec.c

core/ir/aarch64/codec.py

core/ir/opnd_shared.c

core/lib/globals_api.h

ext/drstatecmp/drstatecmp.c

- Change int register types to enum reg_type. - Make vector length getter function SVE and SIMD neutral, i.e. proc_get_sve_vector_length_bytes() -> proc_get_vector_length_bytes(). - Functions name changes. - More informative comments.

…nch update.

…codec.py

…_reg() and append_restore_simd_reg()

…ling.

…bank.

- Updated release notes to include compatibility-affecting changes due to dr_mcontext_t and dr_simd_t support for SVE. - Added binary compatibility machine context size check in priv_mcontext_to_dr_mcontext() for DR_MC_MULTIMEDIA clients in the case of pre-SVE clients. - Made AArch32 SIMD registers comment private (non-Doxygen). - Updated ignore list in runsuite_wrapper.pl for QEMU based regressions, issue #6260.

AssadHashmi · 2023-08-10T19:36:47Z

Raised issue #6260 for #5835 (comment).

api/docs/release.dox

core/arch/arch.c

…release.dox. Updated version numbering in: - Top-level CMakeLists.txt - .github/workflows/ci-docs.yml - .github/workflows/ci-package.yml

core/arch/arch.c

Removed Doxygen link directive, (#dr_simd_t to dr_simd_t) in api/docs/release.dox due to Doxygen parsing error.

This patch adds Arm AArch64 Scalable Vector Extension (SVE) support to the core including related changes to the codec, IR and relevant clients. SVE and SVE2 are major extensions to Arm's 64 bit architecture. Developers and users should reference the relevant documentation at developer.arm.com, (currently https://developer.arm.com/Architectures/Scalable%20Vector%20Extensions). The architecture allows hardware implementations to support vector lengths from 128 to 2048 bits. This patch supports up to 512 bits due to DynamoRIO's stack size limitation. There is currently no stock SVE hardware with vector lengths greater than 512 bits. The vector length is determined by get_processor_specific_info() at runtime on startup and is available by calling proc_get_vector_length(). For Z registers, reg_get_size() will return the vector size implemented by the hardware rather than OPSZ_SCALABLE. There will be follow up patches for: - SVE scatter/gather emulation - Full SVE signal context support - Complete SVE support in sample clients and drcachesim tracer. Issues: #5365, #3044 --------- Co-authored-by: Cam Mannett <camden.mannett@arm.com>

derekbruening · 2023-08-24T15:00:59Z

This PR broke DR on Mac M1 where XPACI is no longer encodeable. I filed PR #6276 on this.

This patch adds SVE support for signals in the core. It is the follow on patch from the SVE core work part 1, in PR #5835 (f646a63) and includes vector address computation for SVE scatter/gather, enabling first-fault load handling. Issue: #5365, #5036 Co-authored-by: Jack Gallagher <jack.gallagher@arm.com>

AssadHashmi added 4 commits January 24, 2023 18:42

Fix source format non-compliances.

462ae72

Remove spurious TAB.

ec3b2d0

Multi-line body error in core/arch/aarchxx/mangle.c

c1d0c06

AssadHashmi requested review from derekbruening and abhinav92003 January 24, 2023 19:30

derekbruening reviewed Jan 24, 2023

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derekbruening reviewed Jan 26, 2023

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AssadHashmi added 20 commits February 23, 2023 13:47

Address some minor review issues, see below:

e30f977

- Change int register types to enum reg_type. - Make vector length getter function SVE and SIMD neutral, i.e. proc_get_sve_vector_length_bytes() -> proc_get_vector_length_bytes(). - Functions name changes. - More informative comments.

Fix reg_type enum declarations.

f5d15fd

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

cbcb088

Resolve merge conflicts due to OPSZ_SVE_VL and OPSZ_SVE_VL_BYTES

734b78e

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

3e80e83

Update dr_get_sve_vl() to dr_get_sve_vector_length() after latest bra…

e65b836

…nch update.

Fix format non-conformances in instr_create_api.h

9d2d1df

Set VL for test builds and revert BUILD_TESTS changes in codec.c and …

69de817

…codec.py

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

85f2110

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

d0d7d71

Add save/restore code for SVE in emit_utils.c

e08b143

Fix source format non-compliances.

565b8f7

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

c8c602c

Use dr_get_sve_vector_length() to read current VL in append_save_simd…

6916889

…_reg() and append_restore_simd_reg()

Use proc_get_vector_length_bytes() NOT dr_get_sve_vector_length()!

799e4af

Add predicate register bank and first pass at predicate register hand…

8dfb2aa

…ling.

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

2317012

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

02d83f0

Adjust machine context size and dstack offset for predicate register …

36bd7cf

…bank.

Add FFR and supporting emitter code for SVE

6863799

AssadHashmi mentioned this pull request Aug 10, 2023

Investigate and fix 3 AArch64 unit test regressions found when executing on QEMU #6260

Open

AssadHashmi added 2 commits August 10, 2023 19:39

Remove spurious TABs in runsuite_wrapper.pl

a3c794e

Multi-line body needs {} in priv_mcontext_to_dr_mcontext()

0532404

AssadHashmi requested a review from derekbruening August 10, 2023 20:11

derekbruening reviewed Aug 11, 2023

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Re-worded and moved binary compatibility text to relevant section in …

3c72817

…release.dox. Updated version numbering in: - Top-level CMakeLists.txt - .github/workflows/ci-docs.yml - .github/workflows/ci-package.yml

AssadHashmi requested a review from derekbruening August 11, 2023 11:42

derekbruening approved these changes Aug 11, 2023

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core/arch/arch.c Outdated Show resolved Hide resolved

Re-worded binary compatibility comment in priv_mcontext_to_dr_mcontext()

b48a441

Removed Doxygen link directive, (#dr_simd_t to dr_simd_t) in api/docs/release.dox due to Doxygen parsing error.

AssadHashmi mentioned this pull request Aug 11, 2023

Doxygen fails to parse and render dr_simd_t to HTML #6264

Open

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

95be63a

derekbruening mentioned this pull request Aug 11, 2023

Add categorization of AARch64 instruction mix #6237

Merged

Merge branch 'master' into i5365-aarch64-sve-veclen-part1

1564258

AssadHashmi added this pull request to the merge queue Aug 14, 2023

AssadHashmi removed this pull request from the merge queue due to a manual request Aug 14, 2023

AssadHashmi changed the title ~~i#5365: Add AArch64 SVE vector length support (part 1)~~ i#5365: Add AArch64 SVE support to the core (part 1) Aug 14, 2023

AssadHashmi added this pull request to the merge queue Aug 14, 2023

github-merge-queue bot removed this pull request from the merge queue due to failed status checks Aug 14, 2023

AssadHashmi merged commit f646a63 into master Aug 14, 2023
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AssadHashmi deleted the i5365-aarch64-sve-veclen-part1 branch August 14, 2023 12:44

derekbruening mentioned this pull request Aug 24, 2023

AArch64 Regression: Failure to encode XPACI after PR #5835 #6276

Open

AssadHashmi mentioned this pull request Sep 21, 2023

AArch64 SVE: complete signal handling support #6317

Open

AssadHashmi mentioned this pull request Nov 13, 2023

OpenMP fails on A64FX (AArch64 SVE) #6451

Open

AssadHashmi mentioned this pull request Mar 26, 2024

i#5365 AArch64 SVE core, part 2: add signals support #6725

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i#5365: Add AArch64 SVE support to the core (part 1) #5835

i#5365: Add AArch64 SVE support to the core (part 1) #5835

AssadHashmi commented Jan 24, 2023 •

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AssadHashmi commented Jan 24, 2023

derekbruening commented Jan 24, 2023

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derekbruening commented Aug 24, 2023

i#5365: Add AArch64 SVE support to the core (part 1) #5835

i#5365: Add AArch64 SVE support to the core (part 1) #5835

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