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i#6662 public traces, part 1: synthetic ISA #6691

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merged 95 commits into from
Apr 10, 2024
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@edeiana edeiana commented Mar 6, 2024

A synthetic ISA that has the purpose of preserving register dependencies and giving
hints on the type of operation an instruction performs. This PR implements the
encoding/decoding functionalities for this new ISA, which we call #DR_ISA_REGDEPS.

Note that being a synthetic ISA, some routines that work on instructions coming from an
actual ISA (such as #DR_ISA_AMD64) are not supported (e.g., decode_sizeof()).

Currently we support:

  • instr_convert_to_isa_regdeps(): to convert an #instr_t of an actual ISA to a
    #DR_ISA_REGDEPS #instr_t.
  • instr_encode() and instr_encode_to_copy(): to encode a #DR_ISA_REGDEPS #instr_t
    into a sequence of contiguous bytes.
  • decode() and decode_from_copy(): to decode an encoded #DR_ISA_REGDEPS instruction
    into an #instr_t.

A #DR_ISA_REGDEPS #instr_t contains the following information:

  • categories: composed by #dr_instr_category_t values, they indicate the type of
    operation performed (e.g., a load, a store, a floating point math operation, a
    branch, etc.). Note that categories are composable, hence more than one category
    can be set. This information can be obtained using instr_get_category().
  • arithmetic flags: we don't distinguish between different flags, we only report if
    at least one arithmetic flag was read (all arithmetic flags will be set to read)
    and/or written (all arithmetic flags will be set to written). This information
    can be obtained using instr_get_arith_flags().
  • number of source and destination operands: we only consider register operands.
    This information can be obtained using instr_num_srcs() and instr_num_dsts().
  • source operation size: is the largest source operand the instruction operates on.
    This information can be obtained by accessing the #instr_t operation_size field.
  • list of register operand identifiers: they are contained in #opnd_t lists,
    separated in source and destination. Note that these #reg_id_t identifiers are
    virtual and it should not be assumed that they belong to any DR_REG_ enum value
    of any specific architecture. These identifiers are meant for tracking register
    dependencies with respect to other #DR_ISA_REGDEPS instructions only. These
    lists can be obtained by walking the #instr_t operands with instr_get_dst() and
    instr_get_src().
  • ISA mode: is always #DR_ISA_REGDEPS. This information can be obtained using
    instr_get_isa_mode().
  • encoding bytes: an array of bytes containing the #DR_ISA_REGDEPS #instr_t
    encoding. Note that this information is present only for decoded instructions
    (i.e., #instr_t generated by decode() or decode_from_copy()). This information
    can be obtained using instr_get_raw_bits().
  • length: the length of the encoded instruction in bytes. Note that this
    information is present only for decoded instructions (i.e., #instr_t generated by
    decode() or decode_from_copy()). This information can be obtained by accessing
    the #instr_t length field.

Note that all routines that operate on #instr_t and #opnd_t are also supported for
#DR_ISA_REGDEPS instructions. However, querying information outside of those
described above (e.g., the instruction opcode with instr_get_opcode()) will return
the zeroed value set by instr_create() or instr_init() when the #instr_t was
created (e.g., instr_get_opcode() would return OP_INVALID).

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instruction that is being decoded.
Also setting the instr_t flags bit to mark the synthetic instruction as
fully decoded.
references as source operands in the encoded synthetic instruction.
Also avoiding duplicate register operands if the same register appears
on different operands (note that we still distinguish between source and
destination operands).
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I think we're almost there; probably just one more round after we finalize the last couple of decisions.

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@edeiana edeiana merged commit 0343305 into master Apr 10, 2024
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@edeiana edeiana deleted the i6662-synthetic-isa branch April 10, 2024 04:35
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2 participants