Group 14 Pipelined RV32I

If desired, please skip ahead to:

1. Repo Structure Explanation
2. Evidence
3. Test instructions

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Quick summary

The result of this coursework is two CPUs: a pipelined, and a single-cycle CPU. Here you will find a fully pipelined RV32I CPU. For the Single-Cycle version, please see the VERSION-2-SINGLE-CYCLE branch. Caching was attempted, but due to time constraints we did not manage to fully implement it. You can, however, find evidence of this work on the repository in the corresponding branches (see below).

Group Details

Name	CID	GitHub	Email	Link to Personal Statement
Nik Lewis	02031260	nlewxxs	nl621@imperial.ac.uk	Nik's Statement
Ana Dimoska	02061746	ADimoska	ad2121@imperial.ac.uk	Ana's Statement
Benedict Short	02019656	BenShort	benedictnjshort@gmail.com	Benedict's Statement
Ahmed Elkouny	01902185	elkouny	ahmedelkouny@hotmail.com	Ahmed's Statement

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Work Split

File Name	Ahmed	Ben	Nik	Ana
ALU.sv		x
control.sv	p		x
ram_i.sv				x
ram_o.sv				x
ram.sv				x
rom.sv	p			x
register_file.sv		x
memory.sv				x
extend.sv	x	x
fetch_reg_file.sv		x
decode_reg_file.sv		x		p
execute_reg_file.sv		x		p
mem_reg_file.sv		x
top.sv (singlecycle)	x		p
top.sv (pipeline)	p	x	x	p
cpu_tb.cpp	x		x
F1Assembly.s	x			x

LEGEND : x = full responsibility; p = partial contribution;

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Repo Structure Explained

• A new branch for each new feature

• a playground branch for each version. This is the branch where the tinkering and debugging is done in. Major required changes are made in separate branches and the playground is updated using either merges or cherry-picks.

• Once a version has been completed, the playground is branched out to a VERSION-<NUMBER>-<NAME> branch and to a new playground for the subsequent version.

Note that nlewxxs (Nik) is named as a contributor on every branch - this is not the case, it is due to README commits to main at the very start setting group rules.

Version name	Explanation
VERSION-1	Partially implemented single cycle, Upper immediate and SH, LHU, LH not implemented (do not test)
VERSION-2-SINGLE-CYCLE	Full implementation of single cycle processor, no AUIPC
VERSION-3-PIPELINED	Full Pipelined implementation, all instructions (up to date in main)

Note that merges are not shown on the diagram to make it easier to read. Control and Memory continued to be worked on even after the Single-Cycle implementation was complete.

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Evidence

Apologies for the shaky video :/

PDF:

pdf_comp.mp4

F1:

f1_comp.mp4

In the test folder, you can find copies of the following:

• The above videos (in case they have not loaded properly)
• VCD trace files for both the PDF and F1 programs

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Testing instructions

1. Clone repo and configure vbuddy.cfg file

This is explained in the guide to set up VBuddy provided at the start of the course. If possible, please also make sure that the flag is set to low before running the f1 program. This prevents bugs in some cases.

2. Execute shell script

This branch has been configured for testing both the F1 and PDF programs in the pipelined processor. To test the F1 program, please run the following shell script:

$ ./f1.sh

And push the trigger to start it. This will run for a maximum of 2000 cycles. Please note that trigger is mapped to the register t0, within the register file.

Or likewise for the pdf distribution calculation,

$ ./pdf.sh

Please note that there is one test-bench, but the shell scripts will configure it accordingly.

I have increased the delay in the F1 slightly to account for it being run on the professor's super fast M1 Silicon. If I have overestimated it and the F1 runs slowly, I do apologise.

When testing the PDF function, the default dataset is the gaussian one. To change this, please go to ram.sv > line 18 and change it manually.

The assembly code that is run is provided in F1Assembly.s and pdf.s, but these are not directly linked to the shell scripts. Therefore, if you wish to run alternate code then the pdf.mem and f1.mem files need to be changed manually, apologies for this.