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The finite state machine scheme is implemented on logic elements and D-triggers. To display information about the input and state of the machine, modules were written on System Verilog.

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EfimAlekseevich/State-machine-on-FPGA-Altera-Cyclone-4

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.gitignore

.gitignore

 
 

README.md

README.md

 
 

Waveform.vwf

Waveform.vwf

 
 

always_one.bsf

always_one.bsf

 
 

digits_tube.bsf

digits_tube.bsf

 
 

frequency_divider.bsf

frequency_divider.bsf

 
 

lab_work2_v4.bdf

lab_work2_v4.bdf

 
 

lab_work2_v4.bsf

lab_work2_v4.bsf

 
 

lab_work2_v4.qsf

lab_work2_v4.qsf

 
 

lab_work2_v4.sv

lab_work2_v4.sv

 
 

lab_work2_v4.sv.bak

lab_work2_v4.sv.bak

 
 

lab_work2_v4_COURSE_WORK_STATE_MACHINE.bdf

lab_work2_v4_COURSE_WORK_STATE_MACHINE.bdf

 
 

lab_work2_v4_COURSE_WORK_STATE_MACHINE.bsf

lab_work2_v4_COURSE_WORK_STATE_MACHINE.bsf

 
 

rattle_delay.bsf

rattle_delay.bsf

 
 

state_switch.bsf

state_switch.bsf

 
 

user_sequence.bsf

user_sequence.bsf

 
 

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The finite state machine scheme is implemented on logic elements and D-triggers. To display information about the input and state of the machine, modules were written on System Verilog.

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