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This repo has some building blocks for various functions in Verilog HDL.

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Efinix-Inc/ip

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ip

DDIO-Implements a soft double-data I/O functionality

I2C - Master: stop condition to be improved - Slave: TODO

Memory-Has some BRAM macros

LFSR-Currently supports 3-bits to 35-bits, other TODO

Mult-Has some multiplier macros

RAM Shift Reg-Implements a BRAM based shift register

Reset-Implements a reset circuit

Shift reg-Pipeline also

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This repo has some building blocks for various functions in Verilog HDL.

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