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[pull] master from llvm:master #18

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Aug 28, 2019
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[pull] master from llvm:master #18

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91864f8
[mach-o] Extend LC_DATA_IN_CODE support to x86_64
rui314 Aug 28, 2019
1c5b143
[MVE] VMOVX patterns
davemgreen Aug 28, 2019
efb8b7b
[lldb] Fix and test completion for ambiguous long options
Teemperor Aug 28, 2019
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50 changes: 42 additions & 8 deletions lld/lib/ReaderWriter/MachO/ArchHandler_x86_64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -181,13 +181,30 @@ class ArchHandler_x86_64 : public ArchHandler {
FindAddressForAtom addressForAtom,
normalized::Relocations &relocs) override;

bool isDataInCodeTransition(Reference::KindValue refKind) override {
return refKind == modeCode || refKind == modeData;
}

Reference::KindValue dataInCodeTransitionStart(
const MachODefinedAtom &atom) override {
return modeData;
}

Reference::KindValue dataInCodeTransitionEnd(
const MachODefinedAtom &atom) override {
return modeCode;
}

private:
static const Registry::KindStrings _sKindStrings[];
static const StubInfo _sStubInfo;

enum X86_64Kind: Reference::KindValue {
invalid, /// for error condition

modeCode, /// Content starting at this offset is code.
modeData, /// Content starting at this offset is data.

// Kinds found in mach-o .o files:
branch32, /// ex: call _foo
ripRel32, /// ex: movq _foo(%rip), %rax
Expand Down Expand Up @@ -242,24 +259,34 @@ class ArchHandler_x86_64 : public ArchHandler {
};

const Registry::KindStrings ArchHandler_x86_64::_sKindStrings[] = {
LLD_KIND_STRING_ENTRY(invalid), LLD_KIND_STRING_ENTRY(branch32),
LLD_KIND_STRING_ENTRY(ripRel32), LLD_KIND_STRING_ENTRY(ripRel32Minus1),
LLD_KIND_STRING_ENTRY(ripRel32Minus2), LLD_KIND_STRING_ENTRY(ripRel32Minus4),
LLD_KIND_STRING_ENTRY(invalid),
LLD_KIND_STRING_ENTRY(modeCode),
LLD_KIND_STRING_ENTRY(modeData),
LLD_KIND_STRING_ENTRY(branch32),
LLD_KIND_STRING_ENTRY(ripRel32),
LLD_KIND_STRING_ENTRY(ripRel32Minus1),
LLD_KIND_STRING_ENTRY(ripRel32Minus2),
LLD_KIND_STRING_ENTRY(ripRel32Minus4),
LLD_KIND_STRING_ENTRY(ripRel32Anon),
LLD_KIND_STRING_ENTRY(ripRel32Minus1Anon),
LLD_KIND_STRING_ENTRY(ripRel32Minus2Anon),
LLD_KIND_STRING_ENTRY(ripRel32Minus4Anon),
LLD_KIND_STRING_ENTRY(ripRel32GotLoad),
LLD_KIND_STRING_ENTRY(ripRel32GotLoadNowLea),
LLD_KIND_STRING_ENTRY(ripRel32Got), LLD_KIND_STRING_ENTRY(ripRel32Tlv),
LLD_KIND_STRING_ENTRY(ripRel32Got),
LLD_KIND_STRING_ENTRY(ripRel32Tlv),
LLD_KIND_STRING_ENTRY(lazyPointer),
LLD_KIND_STRING_ENTRY(lazyImmediateLocation),
LLD_KIND_STRING_ENTRY(pointer64), LLD_KIND_STRING_ENTRY(pointer64Anon),
LLD_KIND_STRING_ENTRY(delta32), LLD_KIND_STRING_ENTRY(delta64),
LLD_KIND_STRING_ENTRY(delta32Anon), LLD_KIND_STRING_ENTRY(delta64Anon),
LLD_KIND_STRING_ENTRY(pointer64),
LLD_KIND_STRING_ENTRY(pointer64Anon),
LLD_KIND_STRING_ENTRY(delta32),
LLD_KIND_STRING_ENTRY(delta64),
LLD_KIND_STRING_ENTRY(delta32Anon),
LLD_KIND_STRING_ENTRY(delta64Anon),
LLD_KIND_STRING_ENTRY(negDelta64),
LLD_KIND_STRING_ENTRY(negDelta32),
LLD_KIND_STRING_ENTRY(imageOffset), LLD_KIND_STRING_ENTRY(imageOffsetGot),
LLD_KIND_STRING_ENTRY(imageOffset),
LLD_KIND_STRING_ENTRY(imageOffsetGot),
LLD_KIND_STRING_ENTRY(unwindFDEToFunction),
LLD_KIND_STRING_ENTRY(unwindInfoToEhFrame),
LLD_KIND_STRING_ENTRY(tlvInitSectionOffset),
Expand Down Expand Up @@ -601,6 +628,8 @@ void ArchHandler_x86_64::applyFixupFinal(
case negDelta32:
*loc32 = fixupAddress - targetAddress + ref.addend();
return;
case modeCode:
case modeData:
case lazyPointer:
// Do nothing
return;
Expand Down Expand Up @@ -720,6 +749,8 @@ void ArchHandler_x86_64::applyFixupRelocatable(const Reference &ref,
case unwindInfoToEhFrame:
llvm_unreachable("fixup implies __unwind_info");
return;
case modeCode:
case modeData:
case unwindFDEToFunction:
// Do nothing for now
return;
Expand All @@ -743,6 +774,9 @@ void ArchHandler_x86_64::appendSectionRelocations(
assert(ref.kindArch() == Reference::KindArch::x86_64);
uint32_t sectionOffset = atomSectionOffset + ref.offsetInAtom();
switch (static_cast<X86_64Kind>(ref.kindValue())) {
case modeCode:
case modeData:
return;
case branch32:
appendReloc(relocs, sectionOffset, symbolIndexForAtom(*ref.target()), 0,
X86_64_RELOC_BRANCH | rPcRel | rExtern | rLength4);
Expand Down
7 changes: 7 additions & 0 deletions lldb/packages/Python/lldbsuite/test/functionalities/completion/TestCompletion.py
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Original file line number Diff line number Diff line change
Expand Up @@ -90,6 +90,13 @@ def test_process_launch_arch(self):
['mips',
'arm64'])

@skipIfFreeBSD # timing out on the FreeBSD buildbot
def test_ambiguous_long_opt(self):
self.completions_match('breakpoint modify --th',
['--thread-id',
'--thread-index',
'--thread-name'])

@skipIfFreeBSD # timing out on the FreeBSD buildbot
def test_plugin_load(self):
self.complete_from_to('plugin load ', [])
Expand Down
10 changes: 10 additions & 0 deletions lldb/packages/Python/lldbsuite/test/lldbtest.py
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Expand Up @@ -2194,6 +2194,16 @@ def complete_from_to(self, str_input, patterns, turn_off_re_match=False):
compare_string, msg=COMPLETION_MSG(
str_input, p, match_strings), exe=False, patterns=[p])

def completions_match(self, command, completions):
"""Checks that the completions for the given command are equal to the
given list of completions"""
interp = self.dbg.GetCommandInterpreter()
match_strings = lldb.SBStringList()
interp.HandleCompletion(command, len(command), 0, -1, match_strings)
# match_strings is a 1-indexed list, so we have to slice...
self.assertItemsEqual(completions, list(match_strings)[1:],
"List of returned completion is wrong")

def filecheck(
self,
command,
Expand Down
14 changes: 4 additions & 10 deletions lldb/source/Interpreter/Options.cpp
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Expand Up @@ -706,17 +706,11 @@ bool Options::HandleOptionCompletion(CompletionRequest &request,
// elements
// that are not unique up to this point. getopt_long_only does
// shortest unique match for long options already.

if (cur_opt_str.startswith("--")) {
if (cur_opt_str.consume_front("--")) {
for (auto &def : opt_defs) {
if (!def.long_option)
continue;

if (cur_opt_str.startswith(def.long_option)) {
std::string full_name("--");
full_name.append(def.long_option);
request.AddCompletion(full_name);
}
llvm::StringRef long_option(def.long_option);
if (long_option.startswith(cur_opt_str))
request.AddCompletion("--" + long_option.str());
}
}
return true;
Expand Down
8 changes: 6 additions & 2 deletions llvm/lib/Target/ARM/ARMInstrMVE.td
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Expand Up @@ -1346,8 +1346,12 @@ let Predicates = [HasMVEInt] in {

def : Pat<(insertelt (v8f16 MQPR:$src1), HPR:$src2, imm:$lane),
(MVE_VMOV_to_lane_16 MQPR:$src1, (COPY_TO_REGCLASS HPR:$src2, rGPR), imm:$lane)>;
def : Pat<(extractelt (v8f16 MQPR:$src), imm:$lane),
(COPY_TO_REGCLASS (MVE_VMOV_from_lane_u16 MQPR:$src, imm:$lane), HPR)>;
def : Pat<(extractelt (v8f16 MQPR:$src), imm_even:$lane),
(EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_even:$lane))>;
def : Pat<(extractelt (v8f16 MQPR:$src), imm_odd:$lane),
(COPY_TO_REGCLASS
(VMOVH (EXTRACT_SUBREG MQPR:$src, (SSubReg_f16_reg imm_odd:$lane))),
HPR)>;

def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
(INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
Expand Down
138 changes: 45 additions & 93 deletions llvm/test/CodeGen/Thumb2/mve-div-expand.ll
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Expand Up @@ -932,60 +932,36 @@ entry:
define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-LABEL: fdiv_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov.u16 r1, q1[1]
; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vmov.u16 r0, q0[0]
; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vmov.u16 r2, q0[1]
; CHECK-NEXT: vdiv.f16 s8, s10, s8
; CHECK-NEXT: vmov s10, r2
; CHECK-NEXT: vdiv.f16 s8, s0, s4
; CHECK-NEXT: vmovx.f16 s10, s0
; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov s8, r1
; CHECK-NEXT: vmovx.f16 s8, s4
; CHECK-NEXT: vdiv.f16 s8, s10, s8
; CHECK-NEXT: vdiv.f16 s12, s1, s5
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: vmov.16 q2[0], r0
; CHECK-NEXT: vmov.u16 r0, q1[2]
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmovx.f16 s12, s5
; CHECK-NEXT: vmovx.f16 s14, s1
; CHECK-NEXT: vmov.16 q2[1], r1
; CHECK-NEXT: vmov s12, r0
; CHECK-NEXT: vmov.u16 r0, q0[2]
; CHECK-NEXT: vmov s14, r0
; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[2], r0
; CHECK-NEXT: vmov.u16 r0, q1[3]
; CHECK-NEXT: vmov s12, r0
; CHECK-NEXT: vmov.u16 r0, q0[3]
; CHECK-NEXT: vmov s14, r0
; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vdiv.f16 s12, s2, s6
; CHECK-NEXT: vmov.16 q2[3], r0
; CHECK-NEXT: vmov.u16 r0, q1[4]
; CHECK-NEXT: vmov s12, r0
; CHECK-NEXT: vmov.u16 r0, q0[4]
; CHECK-NEXT: vmov s14, r0
; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov.u16 r0, q1[5]
; CHECK-NEXT: vmov s12, r0
; CHECK-NEXT: vmov.u16 r0, q0[5]
; CHECK-NEXT: vmov s14, r0
; CHECK-NEXT: vmovx.f16 s12, s6
; CHECK-NEXT: vmovx.f16 s14, s2
; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov.16 q2[4], r0
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vdiv.f16 s12, s3, s7
; CHECK-NEXT: vmovx.f16 s4, s7
; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmov.16 q2[5], r0
; CHECK-NEXT: vmov.u16 r0, q1[6]
; CHECK-NEXT: vmov s12, r0
; CHECK-NEXT: vmov.u16 r0, q0[6]
; CHECK-NEXT: vmov s14, r0
; CHECK-NEXT: vdiv.f16 s12, s14, s12
; CHECK-NEXT: vmov r0, s12
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov.u16 r0, q1[7]
; CHECK-NEXT: vmov s4, r0
; CHECK-NEXT: vmov.u16 r0, q0[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vdiv.f16 s0, s0, s4
; CHECK-NEXT: vmov.16 q2[6], r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q2[7], r0
; CHECK-NEXT: vmov q0, q2
Expand All @@ -1005,25 +981,19 @@ define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-NEXT: .pad #64
; CHECK-NEXT: sub sp, #64
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov.u16 r0, q1[0]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[0]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vmov q5, q1
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vstr s2, [sp, #56]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s16
; CHECK-NEXT: vstr s0, [sp, #56]
; CHECK-NEXT: vcvtb.f32.f16 s0, s20
; CHECK-NEXT: vstr s0, [sp, #60]
; CHECK-NEXT: ldrd r0, r1, [sp, #56]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q5[1]
; CHECK-NEXT: vmovx.f16 s2, s16
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[1]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmov r4, s0
; CHECK-NEXT: vmovx.f16 s0, s20
; CHECK-NEXT: vstr s2, [sp, #48]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstr s0, [sp, #52]
Expand All @@ -1033,85 +1003,67 @@ define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
; CHECK-NEXT: vmov.16 q6[0], r4
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: vmov.u16 r0, q5[2]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[2]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vstr s2, [sp, #40]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s17
; CHECK-NEXT: vstr s0, [sp, #40]
; CHECK-NEXT: vcvtb.f32.f16 s0, s21
; CHECK-NEXT: vstr s0, [sp, #44]
; CHECK-NEXT: vmov.16 q6[1], r0
; CHECK-NEXT: ldrd r0, r1, [sp, #40]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmovx.f16 s2, s17
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: vmov.u16 r0, q5[3]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[3]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s21
; CHECK-NEXT: vstr s2, [sp, #32]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstr s0, [sp, #36]
; CHECK-NEXT: vmov.16 q6[2], r0
; CHECK-NEXT: ldrd r0, r1, [sp, #32]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: vmov.u16 r0, q5[4]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[4]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vstr s2, [sp, #24]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s18
; CHECK-NEXT: vstr s0, [sp, #24]
; CHECK-NEXT: vcvtb.f32.f16 s0, s22
; CHECK-NEXT: vstr s0, [sp, #28]
; CHECK-NEXT: vmov.16 q6[3], r0
; CHECK-NEXT: ldrd r0, r1, [sp, #24]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmovx.f16 s2, s18
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: vmov.u16 r0, q5[5]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[5]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s22
; CHECK-NEXT: vstr s2, [sp, #16]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstr s0, [sp, #20]
; CHECK-NEXT: vmov.16 q6[4], r0
; CHECK-NEXT: ldrd r0, r1, [sp, #16]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: vmov.u16 r0, q5[6]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[6]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vstr s2, [sp, #8]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s19
; CHECK-NEXT: vstr s0, [sp, #8]
; CHECK-NEXT: vcvtb.f32.f16 s0, s23
; CHECK-NEXT: vstr s0, [sp, #12]
; CHECK-NEXT: vmov.16 q6[5], r0
; CHECK-NEXT: ldrd r0, r1, [sp, #8]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmovx.f16 s2, s19
; CHECK-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: vmov.u16 r0, q5[7]
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov.u16 r0, q4[7]
; CHECK-NEXT: vmov s2, r0
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmovx.f16 s0, s23
; CHECK-NEXT: vstr s2, [sp]
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-NEXT: vstr s0, [sp, #4]
; CHECK-NEXT: vmov.16 q6[6], r0
; CHECK-NEXT: ldrd r0, r1, [sp]
; CHECK-NEXT: bl fmodf
; CHECK-NEXT: vmov s0, r0
Expand Down
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