rfnoc: Read cmd FIFO size from blocks & configure ctrl_iface

This requires noc_shell compat number 6.0. It will allow sending as many
command packets, but no more, than there is space.

Updated FPGA images for devices:
- X310/X300
- N300/N310/N320
- E310/E320

host/include/uhd/rfnoc/constants.hpp

@@ -24,8 +24,8 @@ static const std::string XML_PATH_ENV = "UHD_RFNOC_DIR";
 //! If the block name can't be automatically detected, this name is used
 static const std::string DEFAULT_BLOCK_NAME = "Block";
 static const uint64_t DEFAULT_NOC_ID        = 0xFFFFFFFFFFFFFFFF;
-static const size_t NOC_SHELL_COMPAT_MAJOR  = 5;
-static const size_t NOC_SHELL_COMPAT_MINOR  = 1;
+static const size_t NOC_SHELL_COMPAT_MAJOR  = 6;
+static const size_t NOC_SHELL_COMPAT_MINOR  = 0;
 
 static const size_t MAX_PACKET_SIZE     = 8000; // bytes
 static const size_t DEFAULT_PACKET_SIZE = 1456; // bytes

host/lib/include/uhdlib/rfnoc/ctrl_iface.hpp

@@ -59,6 +59,17 @@ class ctrl_iface
             const bool readback=false,
             const uint64_t timestamp=0
     ) = 0;
+
+    /*! Set the depth of the command FIFO size
+     *
+     * Note: This is not safe to call during operations. Call this during
+     * initialization.
+     *
+     * \param num_lines The number of lines of depth in the command FIFO. The
+     *                  function will calculate the number of packets that will
+     *                  fit into the command FIFO.
+     */
+    virtual void set_cmd_fifo_size(const size_t num_lines) = 0;
 };
 
 }} /* namespace uhd::rfnoc */

host/lib/rfnoc/block_ctrl_base.cpp

@@ -21,6 +21,7 @@
 #include <boost/format.hpp>
 #include <chrono>
 #include <thread>
+
 using namespace uhd;
 using namespace uhd::rfnoc;
 using std::string;
@@ -94,16 +95,20 @@ block_ctrl_base::block_ctrl_base(const make_args_t& make_args)
         // Set source addresses:
         sr_write(SR_BLOCK_SID, get_address(ctrl_port), ctrl_port);
         // Set sink buffer sizes:
-        settingsbus_reg_t reg_fifo = SR_READBACK_REG_FIFOSIZE;
-        size_t buf_size_bytes      = size_t(sr_read64(reg_fifo, ctrl_port));
-        if (buf_size_bytes > 0)
+        const uint64_t fifo_size_reg = sr_read64(SR_READBACK_REG_FIFOSIZE, ctrl_port);
+        const size_t buf_size_bytes  = size_t(fifo_size_reg & 0xFFFFFFFF);
+        if (buf_size_bytes > 0) {
             n_valid_input_buffers++;
+        }
         _tree->create<size_t>(_root_path / "input_buffer_size" / ctrl_port)
             .set(buf_size_bytes);
         // Set MTU size and convert to bytes:
         settingsbus_reg_t reg_mtu = SR_READBACK_REG_MTU;
         size_t mtu                = 8 * (1 << size_t(sr_read64(reg_mtu, ctrl_port)));
         _tree->create<size_t>(_root_path / "mtu" / ctrl_port).set(mtu);
+        // Set command FIFO size
+        const uint32_t cmd_fifo_size = (fifo_size_reg >> 32) & 0xFFFFFFFF;
+        _ctrl_ifaces[ctrl_port]->set_cmd_fifo_size(cmd_fifo_size);
         // Set default destination SIDs
         // Otherwise, the default is someone else's SID, which we don't want
         sr_write(SR_RESP_IN_DST_SID, 0xFFFF, ctrl_port);

host/lib/rfnoc/ctrl_iface.cpp

@@ -66,6 +66,15 @@ template <uhd::endianness_t _endianness> class ctrl_iface_impl : public ctrl_ifa
             readback, bool(timestamp != 0) ? MASSIVE_TIMEOUT : ACK_TIMEOUT);
     }
 
+    void set_cmd_fifo_size(const size_t num_lines)
+    {
+        _max_outstanding_acks =
+            std::min(num_lines / 3, _xports.recv->get_num_recv_frames());
+        UHD_LOG_TRACE("RFNOC",
+            "[ctrl_iface " << _name << "] Changed cmd FIFO size to "
+                           << _max_outstanding_acks);
+    }
+
 private:
     // This is the buffer type for response messages
     struct resp_buff_type
@@ -216,7 +225,7 @@ template <uhd::endianness_t _endianness> class ctrl_iface_impl : public ctrl_ifa
     const std::string _name;
     size_t _seq_out;
     std::queue<size_t> _outstanding_seqs;
-    const size_t _max_outstanding_acks;
+    size_t _max_outstanding_acks;
 
     boost::mutex _mutex;
 };

host/tests/common/mock_ctrl_iface_impl.hpp

@@ -23,5 +23,7 @@ class mock_ctrl_iface_impl : public uhd::rfnoc::ctrl_iface
         const size_t data,
         const bool readback      = false,
         const uint64_t timestamp = 0);
+
+    void set_cmd_fifo_size(const size_t) {}
 };
-#endif /* INCLUDED_MOCK_CTRL_IFACE_IMPL_HPP */
+#endif /* INCLUDED_MOCK_CTRL_IFACE_IMPL_HPP */

images/manifest.txt

@@ -1,16 +1,16 @@
 # UHD Image Manifest File
 # Target    hash    url     SHA256
 # X300-Series
-x3xx_x310_fpga_default          fpga-4bc2c6f       x3xx/fpga-4bc2c6f/x3xx_x310_fpga_default-g4bc2c6f.zip                 6da3dd72b8d409c085c4124cca9e2f84f42f3fbd91adba8bae2e5ddfa9138cb1
-x3xx_x300_fpga_default          fpga-4bc2c6f       x3xx/fpga-4bc2c6f/x3xx_x300_fpga_default-g4bc2c6f.zip                 dcf969eda4da765b7d3cf30fcde31fa592cc2c2fdbb2246f56b39c28ae8d0822
+x3xx_x310_fpga_default          fpga-fe9dcb6       x3xx/fpga-fe9dcb6/x3xx_x310_fpga_default-gfe9dcb6.zip                 07fa23ad6bbd3748e3be71b4ccd3a63324fa2bde711492d2d9f78da0503318af
+x3xx_x300_fpga_default          fpga-fe9dcb6       x3xx/fpga-fe9dcb6/x3xx_x300_fpga_default-gfe9dcb6.zip                 37e29b6c4a76f2a6d9d5325f968dca45910b48188eaf676a3f96a5eecd93fbdc
 # Example daughterboard targets (none currently exist)
 #x3xx_twinrx_cpld_default   example_target
 #dboard_ubx_cpld_default    example_target
 
 # E-Series
-e3xx_e310_sg1_fpga_default      fpga-f52a643       e3xx/fpga-f52a643/e3xx_e310_sg1_fpga_default-gf52a643.zip                 03450918a7c312d53926f3318ea91a57162c545ada4058b9e83a4e0efd4755a4
-e3xx_e310_sg3_fpga_default      fpga-f52a643       e3xx/fpga-f52a643/e3xx_e310_sg3_fpga_default-gf52a643.zip                 e8264dd48c3c3f6e65c8e5ef34a3629aa79a3f17ba845659e553bdcf3dfac303
-e3xx_e320_fpga_default          fpga-4bc2c6f       e3xx/fpga-4bc2c6f/e3xx_e320_fpga_default-g4bc2c6f.zip                 0def19fda1041866273c09d3bacc7e2dba916b8848c8a17a85fecd04009bab73
+e3xx_e310_sg1_fpga_default      fpga-fe9dcb6       e3xx/fpga-fe9dcb6/e3xx_e310_sg1_fpga_default-gfe9dcb6.zip                 a0200f38f40e6062648a9463213e99443ee08a8460ed1da37103d318978fc112
+e3xx_e310_sg3_fpga_default      fpga-fe9dcb6       e3xx/fpga-fe9dcb6/e3xx_e310_sg3_fpga_default-gfe9dcb6.zip                 128a5fbee6cffaec5a498fa49ddf00a5e5f8c54ea703ece7037f1b041b6b377c
+e3xx_e320_fpga_default          fpga-fe9dcb6       e3xx/fpga-fe9dcb6/e3xx_e320_fpga_default-gfe9dcb6.zip                 0902a9014caf9a7b8b0d45df81b5eb32ee06f9f4402d720cce0cd70bb059fdfb
 
 # E310 Filesystems
 e3xx_e310_sdk_default         meta-ettus-v3.15.0.0-e310_prerelease  e3xx/meta-ettus-v3.15.0.0-e310_prerelease/e3xx_e310_sdk_default-v3.15.0.0-e310_prerelease.zip       0
@@ -25,9 +25,9 @@ e3xx_e320_mender_default      meta-ettus-v3.14.0.0-rc1  e3xx/meta-ettus-v3.14.0.
 e3xx_e320_sdimg_default       meta-ettus-v3.14.0.0-rc1  e3xx/meta-ettus-v3.14.0.0-rc1/e3xx_e320_sdimg_default-v3.14.0.0-rc1.zip     0
 
 # N300-Series
-n3xx_n310_fpga_default          fpga-4bc2c6f       n3xx/fpga-4bc2c6f/n3xx_n310_fpga_default-g4bc2c6f.zip                 bbe7d43c098aa847fa656d22a2c0f0d6d8e499e3d2267842d1a01591645b1472
-n3xx_n300_fpga_default          fpga-4bc2c6f       n3xx/fpga-4bc2c6f/n3xx_n300_fpga_default-g4bc2c6f.zip                 1d192a5a07601eb9b229ee604cf9ba7b32ea4fefe7b6e218a18d31f4c1f07b0a
-n3xx_n320_fpga_default          fpga-4bc2c6f        n3xx/fpga-4bc2c6f/n3xx_n320_fpga_default-g4bc2c6f.zip                0ef6414a13b6476d3cf015021ec979e75e4e20349b497cfb2ac9affdc4293a90
+n3xx_n310_fpga_default          fpga-fe9dcb6       n3xx/fpga-fe9dcb6/n3xx_n310_fpga_default-gfe9dcb6.zip                 5e4a412c18da9530a5adfb929c385e184e1eb4581793887ae76159974df034dc
+n3xx_n300_fpga_default          fpga-fe9dcb6       n3xx/fpga-fe9dcb6/n3xx_n300_fpga_default-gfe9dcb6.zip                 3b7ed905939600b3d1c00ebec903e9b5566feb5872fb4eca6920173c8de476a8
+n3xx_n320_fpga_default          fpga-fe9dcb6        n3xx/fpga-fe9dcb6/n3xx_n320_fpga_default-gfe9dcb6.zip                b2f96cf9d2a522a399e9318f7849d8bbf5314ed9a003a362e36528925e16e261
 n3xx_n310_cpld_default          fpga-6bea23d        n3xx/fpga-6bea23d/n3xx_n310_cpld_default-g6bea23d.zip                ef128dcd265ee8615b673021d4ee84c39357012ffe8b28c8ad7f893f9dcb94cb
 n3xx_n320_cpld_default          fpga-4bc2c6f       n3xx/fpga-4bc2c6f/n3xx_n320_cpld_default-g4bc2c6f.zip              6680a9363efc5fa8b5a68beb3dff44f2e314b94e716e3a1751aba0fed1f384da
 # N3XX Mykonos firmware