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At the moment, the EzSBC board has a 100k pull-down "R2-2" that is in conflict with the internal pull-up on SWCLK. One can see that the signal is mid-scale by probing the signal. CMOS inputs generally don't like mid-scale signals, and this resultant resistor divider circuit adds a bit more current consumption too.
A pull-down is not desirable, as the SAMD21 has a feature called "CPU reset extension" (see Section 13.6.2) where SWCLK is sampled when the external reset is triggered. That is why section 39.1.1 of the SAMD21 datasheet states "a pull-up resistor on the SWCLK pin is critical for reliable operations".
So, perhaps it is worth considering replacing the pull-down with a pull-up?
The text was updated successfully, but these errors were encountered:
Thanks for the info. The board needs a revision to isolate the battery sense resistors in sleep mode. I will revise it soon and fix this issue.
I have been looking for the cause of high sleep current on the board. Nothing really excessive but higher than the datasheet numbers. I have duplicated the core in a few places on customer specific boards and it is reliable.
Daniel
Jul 18, 2021 12:41:30 PM majbthrd ***@***.***>:
Just a friendly FYI for any future PCB revisions:
At the moment, the EzSBC board has a 100k pull-down "R2-2" that is in conflict with the internal pull-up on SWCLK. One can see that the signal is mid-scale by probing the signal. CMOS inputs generally don't like mid-scale signals, and this resultant resistor divider circuit adds a bit more current consumption too.
A pull-down is not desirable, as the SAMD21 has a feature called "CPU reset extension" (see Section 13.6.2) where SWCLK is sampled when the external reset is triggered. That is why section 39.1.1 of the SAMD21 datasheet states "a pull-up resistor on the SWCLK pin is critical for reliable operations".
So, perhaps it is worth considering replacing the pull-down with a pull-up?
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Just a friendly FYI for any future PCB revisions:
At the moment, the EzSBC board has a 100k pull-down "R2-2" that is in conflict with the internal pull-up on SWCLK. One can see that the signal is mid-scale by probing the signal. CMOS inputs generally don't like mid-scale signals, and this resultant resistor divider circuit adds a bit more current consumption too.
A pull-down is not desirable, as the SAMD21 has a feature called "CPU reset extension" (see Section 13.6.2) where SWCLK is sampled when the external reset is triggered. That is why section 39.1.1 of the SAMD21 datasheet states "a pull-up resistor on the SWCLK pin is critical for reliable operations".
So, perhaps it is worth considering replacing the pull-down with a pull-up?
The text was updated successfully, but these errors were encountered: