Merge pull request #3560 from bylaws/ec-pt6

FEXCore: Support x64 -> arm64ec calls
FEX-Emu · Apr 9, 2024 · 1a8b61b · 1a8b61b
2 parents f0dad86 + e03434e
commit 1a8b61b
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Showing 16 changed files with 804 additions and 775 deletions.
diff --git a/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp b/FEXCore/Source/Interface/Core/Dispatcher/Dispatcher.cpp
@@ -61,6 +61,9 @@ void Dispatcher::EmitDispatcher() {
 
   ARMEmitter::ForwardLabel l_CTX;
   ARMEmitter::SingleUseForwardLabel l_Sleep;
+#ifdef _M_ARM_64EC
+  ARMEmitter::SingleUseForwardLabel ExitEC;
+#endif
   ARMEmitter::SingleUseForwardLabel l_CompileBlock;
 
   // Push all the register we need to save
@@ -91,7 +94,8 @@ void Dispatcher::EmitDispatcher() {
 
   // Load in our RIP
   // Don't modify TMP3 since it contains our RIP once the block doesn't exist
-
+  // IMPORTANT: Pointers.Common.ExitFunctionEC callsites/implementations need to be
+  // adjusted accordingly if this changes.
   auto RipReg = TMP3;
   ldr(RipReg, STATE_PTR(CpuStateFrame, State.rip));
 
@@ -134,6 +138,10 @@ void Dispatcher::EmitDispatcher() {
 
     // If page pointer is zero then we have no block
     cbz(ARMEmitter::Size::i64Bit, TMP1, &NoBlock);
+#ifdef _M_ARM_64EC
+    // The LSB of an L2 page entry indicates if this page contains EC code
+    tbnz(TMP1, 0, &ExitEC);
+#endif
 
     // Steal the page offset
     and_(ARMEmitter::Size::i64Bit, TMP2, TMP4, 0x0FFF);
@@ -167,6 +175,15 @@ void Dispatcher::EmitDispatcher() {
     }
   }
 
+#ifdef _M_ARM_64EC
+  {
+    Bind(&ExitEC);
+    // Target PC is already loaded into TMP3 at the start of the dispatcher
+    ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+    br(TMP2);
+  }
+#endif
+
   {
     ThreadStopHandlerAddressSpillSRA = GetCursorAddress<uint64_t>();
     SpillStaticRegs(TMP1);

diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/BranchOps.cpp
@@ -53,14 +53,23 @@ DEF_OP(ExitFunction) {
   uint64_t NewRIP;
 
   if (IsInlineConstant(Op->NewRIP, &NewRIP) || IsInlineEntrypointOffset(Op->NewRIP, &NewRIP)) {
-    ARMEmitter::SingleUseForwardLabel l_BranchHost;
-
-    ldr(TMP1, &l_BranchHost);
-    blr(TMP1);
-
-    Bind(&l_BranchHost);
-    dc64(ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker);
-    dc64(NewRIP);
+#ifdef _M_ARM_64EC
+    if (RtlIsEcCode(NewRIP)) {
+      LoadConstant(ARMEmitter::Size::i64Bit, TMP3, NewRIP);
+      ldr(TMP2, STATE_PTR(CpuStateFrame, Pointers.Common.ExitFunctionEC));
+      br(TMP2);
+    } else {
+#endif
+      ARMEmitter::SingleUseForwardLabel l_BranchHost;
+      ldr(TMP1, &l_BranchHost);
+      blr(TMP1);
+
+      Bind(&l_BranchHost);
+      dc64(ThreadState->CurrentFrame->Pointers.Common.ExitFunctionLinker);
+      dc64(NewRIP);
+#ifdef _M_ARM_64EC
+    }
+#endif
   } else {
 
     ARMEmitter::SingleUseForwardLabel FullLookup;

diff --git a/FEXCore/include/FEXCore/Core/CoreState.h b/FEXCore/include/FEXCore/Core/CoreState.h
@@ -243,6 +243,9 @@ namespace FEXCore::Core {
       uint64_t SyscallHandlerFunc{};
       uint64_t ExitFunctionLink{};
 
+      // Handles returning/calling ARM64EC code from the JIT, expects the target PC in TMP3
+      uint64_t ExitFunctionEC{};
+
       uint64_t FallbackHandlerPointers[FallbackHandlerIndex::OPINDEX_MAX];
       uint64_t NamedVectorConstantPointers[FEXCore::IR::NamedVectorConstant::NAMED_VECTOR_CONST_POOL_MAX];
       uint64_t IndexedNamedVectorConstantPointers[FEXCore::IR::IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_MAX];

diff --git a/unittests/InstructionCountCI/FEXOpt/libnss.json b/unittests/InstructionCountCI/FEXOpt/libnss.json
@@ -197,10 +197,10 @@
         "ldr q3, [x11, #272]",
         "ldr q4, [x11]",
         "ldr q5, [x11, #16]",
-        "ldr x0, [x28, #1704]",
+        "ldr x0, [x28, #1712]",
         "ldr q6, [x0, #2832]",
         "tbl v2.16b, {v2.16b}, v6.16b",
-        "ldr x0, [x28, #1704]",
+        "ldr x0, [x28, #1712]",
         "ldr q7, [x0, #432]",
         "tbl v3.16b, {v3.16b}, v7.16b",
         "ldr q8, [x11, #32]",
@@ -281,7 +281,7 @@
         "mov v9.s[2], w25",
         "mov v9.s[1], w20",
         "mov v9.s[0], w22",
-        "ldr x0, [x28, #1704]",
+        "ldr x0, [x28, #1712]",
         "ldr q10, [x0, #224]",
         "tbl v4.16b, {v4.16b}, v10.16b",
         "mov w20, v9.s[1]",