Merge pull request #2186 from lioncash/or

OpcodeDispatcher: Handle VORPD/VORPS/VPOR
FEX-Emu · Nov 29, 2022 · 34e39c9 · 34e39c9
2 parents 4de6902 + 16ed20c
commit 34e39c9
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Showing 6 changed files with 149 additions and 8 deletions.
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5827,6 +5827,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(1, 0b00, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp},
     {OPD(1, 0b01, 0x2B), 1, &OpDispatchBuilder::VMOVVectorNTOp},
 
+    {OPD(1, 0b00, 0x56), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VOR, 16>},
+    {OPD(1, 0b01, 0x56), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VOR, 16>},
+
     {OPD(1, 0b00, 0x57), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VXOR, 16>},
     {OPD(1, 0b01, 0x57), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VXOR, 16>},
 
@@ -5848,8 +5851,9 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(1, 0b01, 0xD6), 1, &OpDispatchBuilder::MOVQOp},
     {OPD(1, 0b01, 0xD7), 1, &OpDispatchBuilder::UnimplementedOp},
 
-    {OPD(1, 0b01, 0xEB), 1, &OpDispatchBuilder::UnimplementedOp},
     {OPD(1, 0b01, 0xE7), 1, &OpDispatchBuilder::VMOVVectorNTOp},
+
+    {OPD(1, 0b01, 0xEB), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VOR, 16>},
     {OPD(1, 0b01, 0xEF), 1, &OpDispatchBuilder::AVXVectorALUOp<IR::OP_VXOR, 16>},
 
     {OPD(2, 0b01, 0x2A), 1, &OpDispatchBuilder::VMOVVectorNTOp},

diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
@@ -409,6 +409,8 @@ void OpDispatchBuilder::AVXVectorALUOp(OpcodeArgs) {
   StoreResult(FPRClass, Op, Result, -1);
 }
 
+template
+void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VOR, 16>(OpcodeArgs);
 template
 void OpDispatchBuilder::AVXVectorALUOp<IR::OP_VXOR, 16>(OpcodeArgs);
 

diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
@@ -62,17 +62,17 @@ void InitializeVEXTables() {
     {OPD(1, 0b00, 0x53), 1, X86InstInfo{"VRCPPS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b10, 0x53), 1, X86InstInfo{"VRCPSS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
 
-    {OPD(1, 0b00, 0x54), 1, X86InstInfo{"VANDPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x54), 1, X86InstInfo{"VANDPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b00, 0x54), 1, X86InstInfo{"VANDPS",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b01, 0x54), 1, X86InstInfo{"VANDPD",    TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
 
     {OPD(1, 0b00, 0x55), 1, X86InstInfo{"VANDNPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0x55), 1, X86InstInfo{"VANDNPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
 
-    {OPD(1, 0b00, 0x56), 1, X86InstInfo{"VORPS",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0x56), 1, X86InstInfo{"VORPD",   TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
+    {OPD(1, 0b00, 0x56), 1, X86InstInfo{"VORPS",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b01, 0x56), 1, X86InstInfo{"VORPD",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(1, 0b00, 0x57), 1, X86InstInfo{"VXORPS",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b01, 0x57), 1, X86InstInfo{"VXORPD",   TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b00, 0x57), 1, X86InstInfo{"VXORPS",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b01, 0x57), 1, X86InstInfo{"VXORPD",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(1, 0b01, 0x60), 1, X86InstInfo{"VPUNPCKLBW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0x61), 1, X86InstInfo{"VPUNPCKLWD", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
@@ -235,7 +235,7 @@ void InitializeVEXTables() {
     {OPD(1, 0b01, 0xE8), 1, X86InstInfo{"VPSUBSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0xE9), 1, X86InstInfo{"VPSUBSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0xEA), 1, X86InstInfo{"VPMINSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
-    {OPD(1, 0b01, 0xEB), 1, X86InstInfo{"VPOR",    TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b01, 0xEB), 1, X86InstInfo{"VPOR",    TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_VEX_1ST_SRC | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b01, 0xEC), 1, X86InstInfo{"VPADDSB", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0xED), 1, X86InstInfo{"VPADDSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0xEE), 1, X86InstInfo{"VPMAXSW", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},

diff --git a/unittests/ASM/VEX/vorpd.asm b/unittests/ASM/VEX/vorpd.asm
@@ -0,0 +1,45 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4142434445464748", "0x5152535455565758", "0x6162636465666768", "0x7172737475767778"],
+    "XMM1": ["0xCCCCCCCC75767778", "0x61626364DDDDDDDD", "0xEEEEEEEE55565758", "0x41424344FFFFFFFF"],
+    "XMM2": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
+    "XMM3": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"],
+    "XMM4": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
+    "XMM5": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data1]
+lea rbx, [rel .data2]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rbx]
+
+; Register only
+vorpd ymm2, ymm0, ymm1
+vorpd xmm3, xmm0, xmm1
+
+; With memory operand
+vorpd ymm4, ymm0, [rbx]
+vorpd xmm5, xmm0, [rbx]
+
+hlt
+
+align 32
+.data1:
+dq 0x4142434445464748
+dq 0x5152535455565758
+dq 0x6162636465666768
+dq 0x7172737475767778
+
+.data2:
+dq 0xCCCCCCCC75767778
+dq 0x61626364DDDDDDDD
+dq 0xEEEEEEEE55565758
+dq 0x41424344FFFFFFFF
diff --git a/unittests/ASM/VEX/vorps.asm b/unittests/ASM/VEX/vorps.asm
@@ -0,0 +1,45 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4142434445464748", "0x5152535455565758", "0x6162636465666768", "0x7172737475767778"],
+    "XMM1": ["0xCCCCCCCC75767778", "0x61626364DDDDDDDD", "0xEEEEEEEE55565758", "0x41424344FFFFFFFF"],
+    "XMM2": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
+    "XMM3": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"],
+    "XMM4": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
+    "XMM5": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data1]
+lea rbx, [rel .data2]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rbx]
+
+; Register only
+vorps ymm2, ymm0, ymm1
+vorps xmm3, xmm0, xmm1
+
+; With memory operand
+vorps ymm4, ymm0, [rbx]
+vorps xmm5, xmm0, [rbx]
+
+hlt
+
+align 32
+.data1:
+dq 0x4142434445464748
+dq 0x5152535455565758
+dq 0x6162636465666768
+dq 0x7172737475767778
+
+.data2:
+dq 0xCCCCCCCC75767778
+dq 0x61626364DDDDDDDD
+dq 0xEEEEEEEE55565758
+dq 0x41424344FFFFFFFF
diff --git a/unittests/ASM/VEX/vpor.asm b/unittests/ASM/VEX/vpor.asm
@@ -0,0 +1,45 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+    "XMM0": ["0x4142434445464748", "0x5152535455565758", "0x6162636465666768", "0x7172737475767778"],
+    "XMM1": ["0xCCCCCCCC75767778", "0x61626364DDDDDDDD", "0xEEEEEEEE55565758", "0x41424344FFFFFFFF"],
+    "XMM2": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
+    "XMM3": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"],
+    "XMM4": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0xEFEEEFEE75767778", "0x71727374FFFFFFFF"],
+    "XMM5": ["0xCDCECFCC75767778", "0x71727374DDDFDFDD", "0x0000000000000000", "0x0000000000000000"]
+  },
+  "MemoryRegions": {
+    "0x100000000": "4096"
+  }
+}
+%endif
+
+lea rdx, [rel .data1]
+lea rbx, [rel .data2]
+
+vmovapd ymm0, [rdx]
+vmovapd ymm1, [rbx]
+
+; Register only
+vpor ymm2, ymm0, ymm1
+vpor xmm3, xmm0, xmm1
+
+; With memory operand
+vpor ymm4, ymm0, [rbx]
+vpor xmm5, xmm0, [rbx]
+
+hlt
+
+align 32
+.data1:
+dq 0x4142434445464748
+dq 0x5152535455565758
+dq 0x6162636465666768
+dq 0x7172737475767778
+
+.data2:
+dq 0xCCCCCCCC75767778
+dq 0x61626364DDDDDDDD
+dq 0xEEEEEEEE55565758
+dq 0x41424344FFFFFFFF