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Merge pull request #3263 from alyssarosenzweig/opt/not-garbage
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OpcodeDispatcher: Make "not" not garbage
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alyssarosenzweig committed Nov 9, 2023
2 parents af32539 + 03087a5 commit 3767f36
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Showing 3 changed files with 53 additions and 26 deletions.
32 changes: 30 additions & 2 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3343,11 +3343,39 @@ void OpDispatchBuilder::NOTOp(OpcodeArgs) {
OrderedNode *DestMem = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.LoadData = false});
DestMem = AppendSegmentOffset(DestMem, Op->Flags);
_AtomicXor(IR::SizeToOpSize(Size), MaskConst, DestMem);
}
else {
} else if (!Op->Dest.IsGPR()) {
// GPR version plays fast and loose with sizes, be safe for memory tho.
OrderedNode *Src = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
Src = _Xor(OpSize::i64Bit, Src, MaskConst);
StoreResult(GPRClass, Op, Src, -1);
} else {
// Specially handle high bits so we can invert in place with the correct
// mask and a larger type.
auto Dest = Op->Dest;
if (Dest.Data.GPR.HighBits) {
LOGMAN_THROW_A_FMT(Size == 1, "Only 8-bit GPRs get high bits");
MaskConst = _Constant(0xFF00);
Dest.Data.GPR.HighBits = false;
}

// Always load full size, we explicitly want the upper bits to get the
// insert behaviour for free/implicitly.
const uint8_t GPRSize = CTX->GetGPRSize();
OrderedNode *Src = LoadSource_WithOpSize(GPRClass, Op, Dest, GPRSize, Op->Flags);

// For 8/16-bit, use 64-bit invert so we invert in place, while getting
// insert behaviour. For 32-bit, use 32-bit invert to zero the upper bits.
unsigned EffectiveSize = Size == 4 ? 4 : GPRSize;

// If we're inverting the whole thing, use Not instead of Xor to save a constant.
if (Size >= 4)
Src = _Not(IR::SizeToOpSize(EffectiveSize), Src);
else
Src = _Xor(IR::SizeToOpSize(EffectiveSize), Src, MaskConst);

// Always store 64-bit, the Not/Xor correctly handle the upper bits and this
// way we can delete the store.
StoreResult_WithOpSize(GPRClass, Op, Dest, Src, GPRSize, -1);
}
}

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8 changes: 3 additions & 5 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
Original file line number Diff line number Diff line change
Expand Up @@ -3081,13 +3081,11 @@
]
},
"not bl": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"eor x20, x20, #0xff",
"bfxil x7, x20, #0, #8"
"eor x7, x7, #0xff"
]
},
"neg bl": {
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39 changes: 20 additions & 19 deletions unittests/InstructionCountCI/PrimaryGroup.json
Original file line number Diff line number Diff line change
Expand Up @@ -3233,13 +3233,19 @@
]
},
"not bl": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"eor x20, x20, #0xff",
"bfxil x7, x20, #0, #8"
"eor x7, x7, #0xff"
]
},
"not bh": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"eor x7, x7, #0xff00"
]
},
"neg bl": {
Expand Down Expand Up @@ -3400,32 +3406,27 @@
]
},
"not bx": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "GROUP2 0xf7 /1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"eor x20, x20, #0xffff",
"bfxil x7, x20, #0, #16"
"eor x7, x7, #0xffff"
]
},
"not ebx": {
"ExpectedInstructionCount": 3,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "GROUP2 0xf7 /1",
"ExpectedArm64ASM": [
"mov w20, w7",
"eor x20, x20, #0xffffffff",
"mov w7, w20"
"mvn w7, w7"
]
},
"not rbx": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "GROUP2 0xf7 /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"eor x7, x7, x20"
"mvn x7, x7"
]
},
"neg bx": {
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