Merge pull request #3395 from pmatos/StaticAnalysis

Code cleanup - mainly dead store removal; NFC
FEX-Emu · Jan 31, 2024 · 6d13d9f · 6d13d9f
2 parents ae7dc25 + e4560ed
commit 6d13d9f
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Showing 8 changed files with 11 additions and 14 deletions.
diff --git a/FEXCore/Source/Interface/Core/Frontend.cpp b/FEXCore/Source/Interface/Core/Frontend.cpp
@@ -284,7 +284,6 @@ void Decoder::DecodeModRM_64(X86Tables::DecodedOperand *Operand, X86Tables::ModR
     if (DisplacementSize == 1) {
       Literal = static_cast<int8_t>(Literal);
     }
-    Displacement = DisplacementSize;
 
     Operand->Type = DecodedOperand::OpType::GPRIndirect;
     Operand->Data.GPRIndirect.GPR = MapModRMToReg(DecodeInst->Flags & DecodeFlags::FLAG_REX_XGPR_B ? 1 : 0, ModRM.rm, false, false, false, false);

diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -316,7 +316,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) {
     _StoreContext(2, GPRClass, NewSegmentSS, offsetof(FEXCore::Core::CPUState, ss_idx));
     UpdatePrefixFromSegment(NewSegmentSS, FEXCore::X86Tables::DecodeFlags::FLAG_SS_PREFIX);
 
-    SP = _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
+    _Add(IR::SizeToOpSize(GPRSize), SP, Constant);
   }
   else {
     // Store the stack in 32-bit mode

diff --git a/FEXCore/Source/Interface/IR/IRParser.cpp b/FEXCore/Source/Interface/IR/IRParser.cpp
@@ -505,8 +505,8 @@ class IRParser: public FEXCore::IR::IREmitter {
       }
 
       if (Def.HasArgs) {
-        RemainingLine = FEXCore::StringUtils::Trim(RemainingLine.substr(CurrentPos));
-        CurrentPos = 0;
+        RemainingLine =
+            FEXCore::StringUtils::Trim(RemainingLine.substr(CurrentPos));
         if (RemainingLine.empty()) {
           // How did we get here?
           Def.HasArgs = false;

diff --git a/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp b/FEXCore/Source/Interface/IR/Passes/DeadContextStoreElimination.cpp
@@ -544,7 +544,8 @@ bool RCLSE::ClassifyContextLoad(FEXCore::IR::IREmitter *IREmit, ContextInfo *Loc
 
 bool RCLSE::ClassifyContextStore(FEXCore::IR::IREmitter *IREmit, ContextInfo *LocalInfo, FEXCore::IR::RegisterClassType Class, uint32_t Offset, uint8_t Size, FEXCore::IR::OrderedNode *CodeNode, FEXCore::IR::OrderedNode *ValueNode) {
   auto Info = FindMemberInfo(LocalInfo, Offset, Size);
-  Info = RecordAccess(Info, Class, Offset, Size, LastAccessType::WRITE, ValueNode, CodeNode);
+  RecordAccess(Info, Class, Offset, Size, LastAccessType::WRITE, ValueNode,
+               CodeNode);
   // TODO: Optimize redundant stores.
   // ContextMemberInfo PreviousMemberInfoCopy = *Info;
   return false;

diff --git a/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp b/FEXCore/Source/Interface/IR/Passes/RegisterAllocationPass.cpp
@@ -1380,8 +1380,9 @@ namespace {
               auto FilledInterference = IREmit->_FillRegister(InterferenceOrderedNode, SpillSlot, InterferenceRegClass);
               FilledInterference.first->Header.Size = InterferenceIROp->Size;
               FilledInterference.first->Header.ElementSize = InterferenceIROp->ElementSize;
-              IREmit->ReplaceUsesWithAfter(InterferenceOrderedNode, FilledInterference, FilledInterference);
-              Spilled = true;
+              IREmit->ReplaceUsesWithAfter(InterferenceOrderedNode,
+                                           FilledInterference,
+                                           FilledInterference);
             }
           }
         }

diff --git a/FEXCore/Source/Utils/ArchHelpers/Arm64.cpp b/FEXCore/Source/Utils/ArchHelpers/Arm64.cpp
@@ -526,9 +526,7 @@ static bool HandleAtomicVectorStore(uint32_t Instr, uintptr_t ProgramCounter) {
   uint32_t *PC = (uint32_t*)ProgramCounter;
 
   uint32_t Size = (Instr >> 30) & 1;
-  uint32_t AddrReg = (Instr >> 5) & 0x1F;
   uint32_t DataReg = Instr & 0x1F;
-  uint32_t DataReg2 = (Instr >> 10) & 0x1F;
 
   if(Size == 1) {
     // 64-bit pair happens on paranoid vector stores
@@ -537,9 +535,9 @@ static bool HandleAtomicVectorStore(uint32_t Instr, uintptr_t ProgramCounter) {
     // [2] cbnz(TMP3, &B); // < Overwritten with DMB
     if (DataReg == 31) {
       uint32_t NextInstr = PC[1];
-      AddrReg = (NextInstr >> 5) & 0x1F;
+      uint32_t AddrReg = (NextInstr >> 5) & 0x1F;
       DataReg = NextInstr & 0x1F;
-      DataReg2 = (NextInstr >> 10) & 0x1F;
+      uint32_t DataReg2 = (NextInstr >> 10) & 0x1F;
       uint32_t STP =
         (0b10 << 30) |
         (0b101001000000000 << 15) |

diff --git a/Source/Tools/CommonTools/HarnessHelpers.h b/Source/Tools/CommonTools/HarnessHelpers.h
@@ -91,7 +91,6 @@ namespace FEX::HarnessHelper {
     if (MatchMask & 1) {
       CheckGPRs("FS", State1.fs_cached, State2.fs_cached);
     }
-    MatchMask >>= 1;
 
     return Matches;
   }

diff --git a/Source/Tools/FEXRootFSFetcher/Main.cpp b/Source/Tools/FEXRootFSFetcher/Main.cpp
@@ -255,12 +255,11 @@ namespace WorkingAppsTester {
       // Scan its output to find the zstd compressor
       FILE *fp = fdopen(fd, "r");
       char *Line {nullptr};
-      ssize_t NumRead;
       size_t Len;
 
       bool ReadingDecompressors = false;
       bool SupportsZSTD = false;
-      while ((NumRead = getline(&Line, &Len, fp)) != -1) {
+      while (getline(&Line, &Len, fp) != -1) {
         if (!ReadingDecompressors) {
           if (strstr(Line, "Decompressors available")) {
             ReadingDecompressors = true;