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Merge pull request #3415 from alyssarosenzweig/opt/testm1
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Optimize test -1
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alyssarosenzweig committed Feb 9, 2024
2 parents 4331753 + 300e272 commit 806e5b8
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Showing 5 changed files with 29 additions and 30 deletions.
7 changes: 7 additions & 0 deletions FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1280,6 +1280,13 @@ void OpDispatchBuilder::TESTOp(OpcodeArgs) {

auto Size = GetDstSize(Op);

// Optimize out masking constants
uint64_t Const;
if (IsValueConstant(WrapNode(Src), &Const)) {
if (Const == (Size == 8 ? ~0ULL : ((1ull << Size * 8) - 1)))
Src = Dest;
}

InvalidateDeferredFlags();

// SF/ZF/CF/OF
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14 changes: 6 additions & 8 deletions unittests/InstructionCountCI/FlagM/Primary.json
Original file line number Diff line number Diff line change
Expand Up @@ -2413,32 +2413,30 @@
"ExpectedInstructionCount": 2,
"Comment": "0xa8",
"ExpectedArm64ASM": [
"and w26, w4, #0xff",
"mov x26, x4",
"cmn wzr, w26, lsl #24"
]
},
"test ax, -1": {
"ExpectedInstructionCount": 2,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"and w26, w4, #0xffff",
"mov x26, x4",
"cmn wzr, w26, lsl #16"
]
},
"test eax, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ands w26, w4, w20"
"ands w26, w4, w4"
]
},
"test rax, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ands x26, x4, x20"
"ands x26, x4, x4"
]
},
"scasb": {
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12 changes: 5 additions & 7 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
Original file line number Diff line number Diff line change
Expand Up @@ -2345,24 +2345,22 @@
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0xffff",
"mov x26, x7",
"cmn wzr, w26, lsl #16"
]
},
"test ebx, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ands w26, w7, w20"
"ands w26, w7, w7"
]
},
"test rbx, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ands x26, x7, x20"
"ands x26, x7, x7"
]
},
"neg bx": {
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14 changes: 6 additions & 8 deletions unittests/InstructionCountCI/Primary.json
Original file line number Diff line number Diff line change
Expand Up @@ -3611,32 +3611,30 @@
"ExpectedInstructionCount": 2,
"Comment": "0xa8",
"ExpectedArm64ASM": [
"and w26, w4, #0xff",
"mov x26, x4",
"cmn wzr, w26, lsl #24"
]
},
"test ax, -1": {
"ExpectedInstructionCount": 2,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"and w26, w4, #0xffff",
"mov x26, x4",
"cmn wzr, w26, lsl #16"
]
},
"test eax, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ands w26, w4, w20"
"ands w26, w4, w4"
]
},
"test rax, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "0xa9",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ands x26, x4, x20"
"ands x26, x4, x4"
]
},
"stosb": {
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12 changes: 5 additions & 7 deletions unittests/InstructionCountCI/PrimaryGroup.json
Original file line number Diff line number Diff line change
Expand Up @@ -2839,24 +2839,22 @@
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"and w26, w7, #0xffff",
"mov x26, x7",
"cmn wzr, w26, lsl #16"
]
},
"test ebx, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ands w26, w7, w20"
"ands w26, w7, w7"
]
},
"test rbx, -1": {
"ExpectedInstructionCount": 2,
"ExpectedInstructionCount": 1,
"Comment": "GROUP2 0xf7 /0",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ands x26, x7, x20"
"ands x26, x7, x7"
]
},
"not bx": {
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