Merge pull request #2145 from lioncash/memload

IR: Remove VLoadMemElement and VStoreMemElement
FEX-Emu · Nov 11, 2022 · 9cee012 · 9cee012
2 parents c8293cb + c713602
commit 9cee012
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Showing 8 changed files with 0 additions and 74 deletions.
diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.cpp
@@ -154,8 +154,6 @@ constexpr OpHandlerArray InterpreterOpHandlers = [] {
   REGISTER_OP(STOREMEM,               StoreMem);
   REGISTER_OP(LOADMEMTSO,             LoadMem);
   REGISTER_OP(STOREMEMTSO,            StoreMem);
-  REGISTER_OP(VLOADMEMELEMENT,        VLoadMemElement);
-  REGISTER_OP(VSTOREMEMELEMENT,       VStoreMemElement);
   REGISTER_OP(CACHELINECLEAR,         CacheLineClear);
   REGISTER_OP(CACHELINEZERO,          CacheLineZero);
 

diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h b/External/FEXCore/Source/Interface/Core/Interpreter/InterpreterOps.h
@@ -181,8 +181,6 @@ namespace FEXCore::CPU {
   DEF_OP(StoreFlag);
   DEF_OP(LoadMem);
   DEF_OP(StoreMem);
-  DEF_OP(VLoadMemElement);
-  DEF_OP(VStoreMemElement);
   DEF_OP(CacheLineClear);
   DEF_OP(CacheLineZero);
 

diff --git a/External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp b/External/FEXCore/Source/Interface/Core/Interpreter/MemoryOps.cpp
@@ -236,36 +236,6 @@ DEF_OP(StoreMem) {
   }
 }
 
-DEF_OP(VLoadMemElement) {
-  auto Op = IROp->C<IR::IROp_VLoadMemElement>();
-  void const *MemData = *GetSrc<void const**>(Data->SSAData, Op->Value);
-
-  memcpy(GDP, GetSrc<void*>(Data->SSAData, Op->Addr), 16);
-  memcpy(reinterpret_cast<void*>(reinterpret_cast<uintptr_t>(GDP) + (Op->Header.ElementSize * Op->Index)),
-    MemData, Op->Header.ElementSize);
-}
-
-DEF_OP(VStoreMemElement) {
-  #define STORE_DATA(x, y) \
-    case x: { \
-      y *MemData = *GetSrc<y**>(Data->SSAData, Op->Value); \
-      memcpy(MemData, &GetSrc<y*>(Data->SSAData, Op->Addr)[Op->Index], sizeof(y)); \
-      break; \
-    }
-
-  auto Op = IROp->C<IR::IROp_VStoreMemElement>();
-  uint8_t OpSize = IROp->Size;
-
-  switch (OpSize) {
-    STORE_DATA(1, uint8_t)
-    STORE_DATA(2, uint16_t)
-    STORE_DATA(4, uint32_t)
-    STORE_DATA(8, uint64_t)
-    default: LOGMAN_MSG_A_FMT("Unhandled StoreMem size"); break;
-  }
-  #undef STORE_DATA
-}
-
 DEF_OP(CacheLineClear) {
   auto Op = IROp->C<IR::IROp_CacheLineClear>();
 

diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h b/External/FEXCore/Source/Interface/Core/JIT/Arm64/JITClass.h
@@ -345,8 +345,6 @@ class Arm64JITCore final : public CPUBackend, public Arm64Emitter  {
   DEF_OP(StoreMemTSO);
   DEF_OP(ParanoidLoadMemTSO);
   DEF_OP(ParanoidStoreMemTSO);
-  DEF_OP(VLoadMemElement);
-  DEF_OP(VStoreMemElement);
   DEF_OP(CacheLineClear);
   DEF_OP(CacheLineZero);
 

diff --git a/External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
@@ -1390,14 +1390,6 @@ DEF_OP(ParanoidStoreMemTSO) {
   }
 }
 
-DEF_OP(VLoadMemElement) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(VStoreMemElement) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
 DEF_OP(CacheLineClear) {
   auto Op = IROp->C<IR::IROp_CacheLineClear>();
 
@@ -1458,8 +1450,6 @@ void Arm64JITCore::RegisterMemoryHandlers() {
     REGISTER_OP(LOADMEMTSO,          LoadMemTSO);
     REGISTER_OP(STOREMEMTSO,         StoreMemTSO);
   }
-  REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
-  REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
   REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
   REGISTER_OP(CACHELINEZERO,       CacheLineZero);
 #undef REGISTER_OP

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h b/External/FEXCore/Source/Interface/Core/JIT/x86_64/JITClass.h
@@ -345,8 +345,6 @@ class X86JITCore final : public CPUBackend, public Xbyak::CodeGenerator {
   DEF_OP(StoreFlag);
   DEF_OP(LoadMem);
   DEF_OP(StoreMem);
-  DEF_OP(VLoadMemElement);
-  DEF_OP(VStoreMemElement);
   DEF_OP(CacheLineClear);
   DEF_OP(CacheLineZero);
 

diff --git a/External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp b/External/FEXCore/Source/Interface/Core/JIT/x86_64/MemoryOps.cpp
@@ -668,14 +668,6 @@ DEF_OP(StoreMem) {
   }
 }
 
-DEF_OP(VLoadMemElement) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
-DEF_OP(VStoreMemElement) {
-  LOGMAN_MSG_A_FMT("Unimplemented");
-}
-
 DEF_OP(CacheLineClear) {
   auto Op = IROp->C<IR::IROp_CacheLineClear>();
 
@@ -718,8 +710,6 @@ void X86JITCore::RegisterMemoryHandlers() {
   REGISTER_OP(STOREMEM,            StoreMem);
   REGISTER_OP(LOADMEMTSO,          LoadMem);
   REGISTER_OP(STOREMEMTSO,         StoreMem);
-  REGISTER_OP(VLOADMEMELEMENT,     VLoadMemElement);
-  REGISTER_OP(VSTOREMEMELEMENT,    VStoreMemElement);
   REGISTER_OP(CACHELINECLEAR,      CacheLineClear);
   REGISTER_OP(CACHELINEZERO,       CacheLineZero);
 #undef REGISTER_OP

diff --git a/External/FEXCore/Source/Interface/IR/IR.json b/External/FEXCore/Source/Interface/IR/IR.json
@@ -471,22 +471,6 @@
         ]
       },
 
-      "FPR = VLoadMemElement u8:#RegisterSize, u8:#ElementSize, FPR:$Value, GPR:$Addr, u8:$Index, u8:$Align{1}": {
-        "Desc": ["Loads an element of size #ElementSize in to $Value from $Addr at $Index"
-                ],
-        "OpClass": "Memory",
-        "DestSize": "RegisterSize",
-        "NumElements": "RegisterSize / ElementSize"
-      },
-
-      "VStoreMemElement u8:#RegisterSize, u8:#ElementSize, FPR:$Value, GPR:$Addr, u8:$Index, u8:$Align": {
-        "Desc": ["Stores an element of size #ElementSize from $Value[$Index] to $Addr"
-                ],
-        "HasSideEffects": true,
-        "DestSize": "ElementSize",
-        "NumElements": "RegisterSize / ElementSize"
-      },
-
       "CacheLineClear GPR:$Addr": {
         "Desc": ["Does a 64 byte cacheline clear at the address specified",
                  "Only clears the data cachelines. Doesn't do any zeroing"