Merge pull request #3280 from Sonicadvance1/rpres_afp_requirement

FEXCore: Disables RPRES until AFP is audited and enabled
FEX-Emu · Nov 27, 2023 · b027113 · b027113
2 parents 389c6b1 + c71492e
commit b027113
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Showing 7 changed files with 5 additions and 113 deletions.
diff --git a/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp b/FEXCore/Source/Interface/Core/ArchHelpers/Arm64Emitter.cpp
@@ -591,6 +591,7 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
     // Disable FPCR.NEP and FPCR.AH
     // NEP(2): Changes ASIMD scalar instructions to insert in to the lower bits of the destination.
     // AH(1):  Changes NaN behaviour in some instructions. Specifically fmin, fmax.
+    //         Also interacts with RPRES to change reciprocal/rsqrt precision from 8-bit mantissa to 12-bit.
     //
     // Additional interesting AFP bits:
     // FIZ(0): Flush Inputs to Zero

diff --git a/FEXCore/Source/Interface/Core/HostFeatures.cpp b/FEXCore/Source/Interface/Core/HostFeatures.cpp
@@ -248,6 +248,8 @@ HostFeatures::HostFeatures() {
 
   // TODO: AFP is disabled until the scalar usage in the codebase can be audited to be working as expected.
   SupportsAFP = false;
+  // RPRES has a dependency on AFP. Disable it until AFP is enabled.
+  SupportsRPRES = false;
 
   if (!SupportsAtomics) {
     WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");

diff --git a/unittests/InstructionCountCI/RPRES/DDD.json b/unittests/InstructionCountCI/RPRES/DDD.json
@@ -2,6 +2,7 @@
   "Features": {
     "Bitness": 64,
     "EnabledHostFeatures": [
+      "AFP",
       "RPRES"
     ],
     "DisabledHostFeatures": [

diff --git a/unittests/InstructionCountCI/RPRES/Secondary.json b/unittests/InstructionCountCI/RPRES/Secondary.json
@@ -2,6 +2,7 @@
   "Features": {
     "Bitness": 64,
     "EnabledHostFeatures": [
+      "AFP",
       "RPRES"
     ],
     "DisabledHostFeatures": [

diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP.json
diff --git a/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json b/unittests/InstructionCountCI/RPRES/Secondary_REP_AFP.json
@@ -14,7 +14,6 @@
     "rsqrtss xmm0, xmm1": {
       "ExpectedInstructionCount": 1,
       "Comment": [
-        "AFP can make this more optimal",
         "0xf3 0x0f 0x52"
       ],
       "ExpectedArm64ASM": [
@@ -24,7 +23,6 @@
     "rcpss xmm0, xmm1": {
       "ExpectedInstructionCount": 1,
       "Comment": [
-        "AFP can make this more optimal",
         "0xf3 0x0f 0x53"
       ],
       "ExpectedArm64ASM": [

diff --git a/unittests/InstructionCountCI/RPRES/VEX_map1.json b/unittests/InstructionCountCI/RPRES/VEX_map1.json