Merge pull request #2171 from lioncash/dqa

OpcodeDispatcher: Handle VMOVDQA/VMOVDQU
FEX-Emu · Nov 22, 2022 · df761a9 · df761a9
2 parents 0030971 + e140c0d
commit df761a9
Show file tree

Hide file tree

Showing 4 changed files with 99 additions and 8 deletions.
diff --git a/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/External/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -5712,18 +5712,19 @@ void OpDispatchBuilder::InstallHostSpecificOpcodeHandlers() {
     {OPD(1, 0b00, 0x29), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op},
     {OPD(1, 0b01, 0x29), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op},
 
-    {OPD(1, 0b01, 0x6E), 2, &OpDispatchBuilder::UnimplementedOp},
+    {OPD(1, 0b01, 0x6E), 1, &OpDispatchBuilder::UnimplementedOp},
 
-    {OPD(1, 0b10, 0x6F), 1, &OpDispatchBuilder::UnimplementedOp},
+    {OPD(1, 0b01, 0x6F), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op},
+    {OPD(1, 0b10, 0x6F), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op},
 
     {OPD(1, 0b01, 0x74), 3, &OpDispatchBuilder::UnimplementedOp},
 
     {OPD(1, 0b00, 0x77), 1, &OpDispatchBuilder::UnimplementedOp},
 
     {OPD(1, 0b01, 0x7E), 1, &OpDispatchBuilder::UnimplementedOp},
 
-    {OPD(1, 0b01, 0x7F), 1, &OpDispatchBuilder::UnimplementedOp},
-    {OPD(1, 0b10, 0x7F), 1, &OpDispatchBuilder::UnimplementedOp},
+    {OPD(1, 0b01, 0x7F), 1, &OpDispatchBuilder::VMOVAPS_VMOVAPD_Op},
+    {OPD(1, 0b10, 0x7F), 1, &OpDispatchBuilder::VMOVUPS_VMOVUPD_Op},
 
     {OPD(1, 0b01, 0xD7), 1, &OpDispatchBuilder::UnimplementedOp},
     {OPD(1, 0b01, 0xEB), 1, &OpDispatchBuilder::UnimplementedOp},

diff --git a/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp b/External/FEXCore/Source/Interface/Core/X86Tables/VEXTables.cpp
@@ -179,8 +179,8 @@ void InitializeVEXTables() {
     {OPD(1, 0b01, 0x6D), 1, X86InstInfo{"VPUNPCKHQDQ", TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b01, 0x6E), 1, X86InstInfo{"VMOV*",       TYPE_INST, GenFlagsDstSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS | FLAGS_SF_SRC_GPR, 0, nullptr}},
 
-    {OPD(1, 0b01, 0x6F), 1, X86InstInfo{"VMOVDQA",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b10, 0x6F), 1, X86InstInfo{"VMOVDQU",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b01, 0x6F), 1, X86InstInfo{"VMOVDQA",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b10, 0x6F), 1, X86InstInfo{"VMOVDQU",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(1, 0b01, 0x7C), 1, X86InstInfo{"VHADDPD",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
     {OPD(1, 0b11, 0x7C), 1, X86InstInfo{"VHADDPS",     TYPE_UNDEC, FLAGS_NONE, 0, nullptr}},
@@ -191,8 +191,8 @@ void InitializeVEXTables() {
     {OPD(1, 0b01, 0x7E), 1, X86InstInfo{"VMOV*",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
     {OPD(1, 0b10, 0x7E), 1, X86InstInfo{"VMOVQ",     TYPE_INST, FLAGS_MODRM | FLAGS_XMM_FLAGS, 0, nullptr}},
 
-    {OPD(1, 0b01, 0x7F), 1, X86InstInfo{"VMOVDQA",     TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
-    {OPD(1, 0b10, 0x7F), 1, X86InstInfo{"VMOVDQU",     TYPE_INST, FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b01, 0x7F), 1, X86InstInfo{"VMOVDQA",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
+    {OPD(1, 0b10, 0x7F), 1, X86InstInfo{"VMOVDQU",     TYPE_INST, GenFlagsSameSize(SIZE_128BIT) | FLAGS_MODRM | FLAGS_SF_MOD_DST | FLAGS_XMM_FLAGS, 0, nullptr}},
 
     {OPD(1, 0b00, 0xAE), 1, X86InstInfo{"",     TYPE_VEX_GROUP_15, FLAGS_NONE, 0, nullptr}}, // VEX Group 15
     {OPD(1, 0b01, 0xAE), 1, X86InstInfo{"",     TYPE_VEX_GROUP_15, FLAGS_NONE, 0, nullptr}}, // VEX Group 15

diff --git a/unittests/ASM/VEX/vmovdqa.asm b/unittests/ASM/VEX/vmovdqa.asm
@@ -0,0 +1,45 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+      "XMM1": ["0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF"],
+      "XMM2": ["0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0x0000000000000000", "0x0000000000000000"],
+      "XMM3": ["0xCCCCCCCCCCCCCCCC", "0xCCCCCCCCCCCCCCCC", "0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD"],
+      "XMM4": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xEEEEEEEEEEEEEEEE", "0xFFFFFFFFFFFFFFFF"],
+      "XMM5": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF"],
+      "XMM6": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xEEEEEEEEEEEEEEEE", "0xFFFFFFFFFFFFFFFF"]
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+; Load inputs
+vmovdqa ymm1, [rdx]
+vmovdqa xmm2, [rdx]
+vmovdqa ymm3, [rdx + 32]
+
+; Test memory overwrite
+mov rax, 0xCCCCCCCCCCCCCCCC
+mov [rdx + 32], rax
+mov rax, 0xDDDDDDDDDDDDDDDD
+mov [rdx + 40], rax
+mov rax, 0xEEEEEEEEEEEEEEEE
+mov [rdx + 48], rax
+mov rax, 0xFFFFFFFFFFFFFFFF
+mov [rdx + 56], rax
+
+vmovdqa ymm4, [rdx + 32]
+vmovdqa [rdx], xmm4
+vmovapd ymm5, [rdx]
+vmovdqa [rdx], ymm4
+vmovapd ymm6, [rdx]
+
+hlt
+
+align 32
+.data:
+db 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+db 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+db 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC
+db 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD
diff --git a/unittests/ASM/VEX/vmovdqu.asm b/unittests/ASM/VEX/vmovdqu.asm
@@ -0,0 +1,45 @@
+%ifdef CONFIG
+{
+  "HostFeatures": ["AVX"],
+  "RegData": {
+      "XMM1": ["0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF"],
+      "XMM2": ["0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF", "0x0000000000000000", "0x0000000000000000"],
+      "XMM3": ["0xCCCCCCCCCCCCCCCC", "0xCCCCCCCCCCCCCCCC", "0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD"],
+      "XMM4": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xEEEEEEEEEEEEEEEE", "0xFFFFFFFFFFFFFFFF"],
+      "XMM5": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xFFFFFFFFFFFFFFFF", "0xFFFFFFFFFFFFFFFF"],
+      "XMM6": ["0xCCCCCCCCCCCCCCCC", "0xDDDDDDDDDDDDDDDD", "0xEEEEEEEEEEEEEEEE", "0xFFFFFFFFFFFFFFFF"]
+  }
+}
+%endif
+
+lea rdx, [rel .data]
+
+; Load inputs
+vmovdqu ymm1, [rdx]
+vmovdqu xmm2, [rdx]
+vmovdqu ymm3, [rdx + 32]
+
+; Test memory overwrite
+mov rax, 0xCCCCCCCCCCCCCCCC
+mov [rdx + 32], rax
+mov rax, 0xDDDDDDDDDDDDDDDD
+mov [rdx + 40], rax
+mov rax, 0xEEEEEEEEEEEEEEEE
+mov [rdx + 48], rax
+mov rax, 0xFFFFFFFFFFFFFFFF
+mov [rdx + 56], rax
+
+vmovdqu ymm4, [rdx + 32]
+vmovdqu [rdx], xmm4
+vmovapd ymm5, [rdx]
+vmovdqu [rdx], ymm4
+vmovapd ymm6, [rdx]
+
+hlt
+
+align 32
+.data:
+db 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+db 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+db 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC
+db 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD