This project is about designing and implementing LZ4 decompression algorithm in hardware using Verilog hardware description language.
For full details, see the report.
This is part of a university course project COE405 Design And Modeling Of Digital Systems at KFUPM with Dr Aimane.
The report discusses the how the project was executed and how we designed the control unit and datapath.
The report also includes tests and simulations to decompress data compressed.
Below is the schematic of the datapath.
More detailed contribution info can be found in the report.
- Faris Hijazi
- Mohammed Bejadi