GitHub - Fernsicles/RV32-verilog: A RV32 CPU and associated simulator implemented in System Verilog.

Fernsicles / RV32-verilog Public

A RV32 CPU and associated simulator implemented in System Verilog.

Notifications

Name		Name	Last commit message	Last commit date
Latest commit History 197 Commits
ELFIO @ ef26228		ELFIO @ ef26228
boards/xc6slx9		boards/xc6slx9
gui		gui
include		include
programs		programs
resources		resources
riscv-disassembler @ 906b28d		riscv-disassembler @ 906b28d
.gitignore		.gitignore
.gitmodules		.gitmodules
ALU.sv		ALU.sv
ALUtest.cpp		ALUtest.cpp
CPU.sv		CPU.sv
CPU_sim.cpp		CPU_sim.cpp
INSTALL		INSTALL
MALU.sv		MALU.sv
Makefile		Makefile
compile.sh		compile.sh
control_unit.sv		control_unit.sv
mmio.txt		mmio.txt
registers.sv		registers.sv
rvgui.gresource.xml		rvgui.gresource.xml