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Expansion Bay Electrical Design

Warning: the documentation here is pretty early, so there may be minor adjustments in the mechanical or electrical designs before the Framework Laptop 16 launches. We'll let you know when the design is locked for production.

License

Expansion Bay © 2023 by Framework Computer Inc is licensed under CC BY 4.0. To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/

Pinout

There are two 74-pin interposers that are connected together to form the Expansion Bay Interface. One is primarily for power, while the other is primarily for PCIe, DisplayPort, and other high speed signals.

Power Interface

Pin No. Signal Name I/O Type Power Domain Impedance Voltage Current Notes Function Column Row
1 VSYS_GPU I Power N/A 7~20V 0.75A Main power rail to Expansion Bay Modules from Vsys. While on battery, Vsys can be as low as 15.2V (3.8Vx4), and sustained current will also be limited. While on AC with a high power adapter, Vsys will be 20V, with maximum current up to 10.5A. However, thermal limits and regulator efficiency could limit the practical maximum power to lower. 8 PA
2 VSYS_GPU I Power N/A 7~20V 0.75A 7 PA
3 VSYS_GPU I Power N/A 7~20V 0.75A 8 PB
4 VSYS_GPU I Power N/A 7~20V 0.75A 7 PB
5 VSYS_GPU I Power N/A 7~20V 0.75A 8 PC
6 VSYS_GPU I Power N/A 7~20V 0.75A 7 PC
7 VSYS_GPU I Power N/A 7~20V 0.75A 8 PD
8 VSYS_GPU I Power N/A 7~20V 0.75A 7 PD
9 VSYS_GPU I Power N/A 7~20V 0.75A 8 PE
10 VSYS_GPU I Power N/A 7~20V 0.75A 7 PE
11 VSYS_GPU I Power N/A 7~20V 0.75A 8 PF
12 VSYS_GPU I Power N/A 7~20V 0.75A 7 PF
13 VSYS_GPU I Power N/A 7~20V 0.75A 8 PG
14 VSYS_GPU I Power N/A 7~20V 0.75A 7 PG
15 GND O GND N/A 0V 0.75A Ground for VSYS_GPU 8 PH
16 GND O GND N/A 0V 0.75A 7 PH
17 GND O GND N/A 0V 0.75A 8 PJ
18 GND O GND N/A 0V 0.75A 7 PJ
19 GND O GND N/A 0V 0.75A 6 PA
20 GND O GND N/A 0V 0.75A 6 PB
21 GND O GND N/A 0V 0.75A 6 PC
22 GND O GND N/A 0V 0.75A 6 PD
23 GND O GND N/A 0V 0.75A 6 PE
24 GND O GND N/A 0V 0.75A 6 PF
25 GND O GND N/A 0V 0.75A 6 PG
26 GND O GND N/A 0V 0.75A 6 PH
27 5V_ALW I Power VS N/A 5V+/-6% 0.75A 5V maximum current consumption is 2.5A 5V power for Expansion Bay Module 8 PK
28 5V_ALW I Power VS N/A 5V+/-6% 0.75A 7 PK
29 5V_ALW I Power VS N/A 5V+/-6% 0.75A 8 PL
30 5V_ALW I Power VS N/A 5V+/-6% 0.75A 7 PL
31 GND O GND N/A 0V 0.75A Ground for 5V 6 PJ
32 GND O GND N/A 0V 0.75A 6 PK
33 GND O GND N/A 0V 0.75A 6 PL
34 3V3_ALW I Power VS N/A 3.3V+/-6% 0.75A 3.3V maximum current consumption is 2.0A 3.3V ALW for Expansion Bay Module 5 PA
35 3V3_ALW I Power VS N/A 3.3V+/-6% 0.75A 4 PA
36 3V3_ALW I Power VS N/A 3.3V+/-6% 0.75A 5 PB
37 3V3_ALW I Power VS N/A 3.3V+/-6% 0.75A 4 PB
38 GND O GND N/A 0V 0.75A Ground for 3.3V_ALW 3 PA
39 GND O GND N/A 0V 0.75A 3 PB
40 GND O GND N/A 0V 0.75A 3 PE
41 VADP_GPU I/O Power N/A 7.6V/20V 0.75A This allows power to be fed from the Expansion Bay back into the laptop in an Extended Battery scenario or another type of card that has a power supply attached. Power path for power input from the Expansion Bay to the host 2 PA
42 VADP_GPU I/O Power N/A 7.6V/20V 0.75A 1 PA
43 VADP_GPU I/O Power N/A 7.6V/20V 0.75A 2 PB
44 VADP_GPU I/O Power N/A 7.6V/20V 0.75A 1 PB
45 VADP_GPU I/O Power N/A 7.6V/20V 0.75A 2 PC
46 VADP_GPU I/O Power N/A 7.6V/20V 0.75A 1 PC
47 GND O GND N/A 0V 0.75A Ground for VADP_GPU 2 PD
48 GND O GND N/A 0V 0.75A 1 PD
49 GND O GND N/A 0V 0.75A 2 PE
50 GND O GND N/A 0V 0.75A 1 PE
51 GND O GND N/A 0V 0.75A 1 PF
52 EXT_SSD1_RST# I/O OD VS N/A 3.3V SSD holder control signal Control external SSD 3 PF
53 EXT_SSD2_RST# I/O OD VS N/A 3.3V 3 PG
54 EXT_SSD2_CLK_REQ# I/O OD VS N/A 3.3V 2 PG
55 GND O GND N/A 0V 0.75A GND for USB isolation Isolation ground 3 PH
56 USB+ I/O I/O VS 90Ohm diff 3.3V Support USB FS and HS USB2.0 Bus 3 PJ
57 USB- I/O I/O VS 90Ohm diff 3.3V 3 PK
58 GND O GND N/A 0V 0.75A GND for USB isolation Isolation ground 3 PL
59 I2C_INT_ALW I/O OD ALW N/A 3.3V I2C with ALW power domain. Connect to EC I2C Bus 2 PF
60 I2C_CLK_ALW I/O OD ALW N/A 3.3V 3 PC
61 I2C_DAT_ALW I/O OD ALW N/A 3.3V 3 PD
62 GPIO0_EC OD CMOS ALW N/A 3.3V Connect to EC GPIO PU for CTF to power down the dGPU I/O pin for 2nd battery 1 PG
63 GPIO1_EC OD CMOS ALW N/A 3.3V Connect to EC GPIO on mainboard, control 2nd battery discharge and DP_HPD from dGPU PD controller 1 PH
64 ID0 O CMOS N/A 3.3V Connect to EC ADC with 100K pull-up to identify if the power connector is well connected 1 PJ
65 12V_FAN I Power N/A 12V 0.75A 12V power for Fan 4 PL
66 Fan0_PWM I CMOS N/A 5V PWM control for Fan. Connect to EC Fan control 5 PL
67 Fan1_PWM I CMOS N/A 5V PWM control for Fan. Connect to EC 5 PK
68 Fan0_SPEED O OD N/A 5V Fan speed for Fan. Connect to EC 2 PH
69 Fan1_SPEED O OD N/A 5V Fan speed for Fan. Connect to EC 2 PJ
70 GND O GND N/A 0V 0.75A Ground for Fan power 4 PK
71 DDS_SDA I OD N/A I2C DATA for DDS Expansion Bay Module control 1 PK
72 PWR_EN I I/O N/A Module power enable, Connect to PCH 2 PK
73 PWR_GOOD O OD N/A Power sequencing sideband, Connect to PCH. When using an Expansion Bay Module that uses two PCIe ports, it will switch to the 2nd PCIe clock request. 1 PL
74 DDS_CLK I/O OD N/A I2C CLK for DDS 2 PL

Signal Interface

Pin No. Signal Name I/O Type Power Domain Impedance Voltage Current Remark Function description Column Row
1 GND O GND N/A 0V 0.75A GND for PCIe isolation PCIe x8 interface 8 SF
2 PEX_TX0 I Diff N/A PCI Express TX Lane0 8 SH
3 PEX_TX0# I Diff N/A 8 SG
4 GND O GND N/A 0V 0.75A GND for PCIe isolation 8 SJ
5 PEX_TX1 I Diff 80-85Ohm diff PCI Express TX Lane1 8 SL
6 PEX_TX1# I Diff 80-85Ohm diff 8 SK
7 GND O GND N/A 0V 0.75A GND for PCIe isolation 7 SH
8 PEX_TX2 I Diff 80-85Ohm diff PCI Express TX Lane2 6 SG
9 PEX_TX2# I Diff 80-85Ohm diff 6 SH
10 GND O GND N/A 0V 0.75A GND for PCIe isolation 6 SF
11 PEX_TX3 I Diff 80-85Ohm diff PCI Express TX Lane3 6 SL
12 PEX_TX3# I Diff 80-85Ohm diff 6 SK
13 GND O GND N/A 0V 0.75A GND for PCIe isolation 6 SJ
14 PEX_TX4 I Diff 80-85Ohm diff PCI Express TX Lane4 3 SK
15 PEX_TX4# I Diff 80-85Ohm diff 3 SL
16 GND O GND N/A 0V 0.75A GND for PCIe isolation 3 SJ
17 PEX_TX5 I Diff 80-85Ohm diff PCI Express TX Lane5 3 SH
18 PEX_TX5# I Diff 80-85Ohm diff 3 SG
19 GND O GND N/A 0V 0.75A GND for PCIe isolation 1 SJ
20 PEX_TX6 I Diff 80-85Ohm diff PCI Express TX Lane6 1 SK
21 PEX_TX6# I Diff 80-85Ohm diff 1 SL
22 GND O GND N/A 0V 0.75A GND for PCIe isolation 2 SH
23 PEX_TX7 I Diff 80-85Ohm diff PCI Express TX Lane7 1 SH
24 PEX_TX7# I Diff 80-85Ohm diff 1 SG
25 GND O GND N/A 0V 0.75A GND for PCIe isolation 1 SF
26 PEX_RX0 O Diff 80-85Ohm diff PCI Express RX Lane0 8 SE
27 PEX_RX0# O Diff 80-85Ohm diff 8 SD
28 GND O GND N/A 0V 0.75A GND for PCIe isolation 8 SC
29 PEX_RX1 O Diff 80-85Ohm diff PCI Express RX Lane1 8 SB
30 PEX_RX1# O Diff 80-85Ohm diff 8 SA
31 GND O GND N/A 0V 0.75A GND for PCIe isolation 7 SE
32 PEX_RX2 O Diff 80-85Ohm diff PCI Express RX Lane2 6 SE
33 PEX_RX2# O Diff 80-85Ohm diff 6 SD
34 GND O GND N/A 0V 0.75A GND for PCIe isolation 7 SB
35 PEX_RX3 O Diff 80-85Ohm diff PCI Express RX Lane3 6 SB
36 PEX_RX3# O Diff 80-85Ohm diff 6 SA
37 GND O GND N/A 0V 0.75A GND for PCIe isolation 6 SC
38 PEX_RX4 O Diff 80-85Ohm diff PCI Express RX Lane4 3 SA
39 PEX_RX4# O Diff 80-85Ohm diff 3 SB
40 GND O GND N/A 0V 0.75A GND for PCIe isolation 3 SC
41 PEX_RX5 O Diff 80-85Ohm diff PCI Express RX Lane5 3 SD
42 PEX_RX5# O Diff 80-85Ohm diff 3 SE
43 GND O GND N/A 0V 0.75A GND for PCIe isolation 3 SF
44 PEX_RX6 O Diff 80-85Ohm diff PCI Express RX Lane6 1 SA
45 PEX_RX6# O Diff 80-85Ohm diff 1 SB
46 GND O GND N/A 0V 0.75A GND for PCIe isolation 1 SC
47 PEX_RX7 O Diff 80-85Ohm diff PCI Express RX Lane7 1 SE
48 PEX_RX7# O Diff 80-85Ohm diff 1 SD
49 GND O GND N/A 0V 0.75A GND for PCIe isolation 2 SB
50 PEX_REFCLK O Diff 90Ohm diff PCI Express reference clock. 2 SC
51 PEX_REFCLK# O Diff 90Ohm diff 2 SD
52 GND O GND N/A 0V 0.75A GND for PCIe isolation 2 SE
53 PEX_RST# I CMOS N/A PCI Express reset signal. 5 SA
54 PEX_CLK_REQ# O OD N/A PCI Express clock request. 4 SA
55 DGPU_PWM_SEL I OD N/A Internal display PWM source select 4 SB
56 DP_A_HPD I CMOS N/A 3.3V DisplayPort A hot plug detect DisplayPort interface for internal display 7 SA
57 DP_A_L0 O Diff 90Ohm diff DisplayPort A Lane0 7 SG
58 DP_A_L0# O Diff 90Ohm diff 7 SF
59 GPIO2_EC I/O CMOS N/A 3.3V Connect to EC GPIO for power switching from AC to DC mode.Connect to GPU GPIO0. Will be high when connected to the PD power source >=180W. 2 SA
60 DP_A_L1 O Diff 90Ohm diff DisplayPort A Lane1 7 SD
61 DP_A_L1# O Diff 90Ohm diff 7 SC
62 PNL_BL_EN O CMOS N/A 3.3V Internal panel backlight enable. Connect to internal display 4 SL
63 DP_A_L2 O Diff 90Ohm diff DisplayPort A Lane2 2 SK
64 DP_A_L2# O Diff 90Ohm diff 2 SJ
65 TH_OVERT# O OD N/A PROCHOT#. Connect to EC. Open collector power/thermal alert. Can drive low to put the system into min power state. Can monitor to put GPU in min power state. 5 SL
66 DP_A_L3 O Diff 90Ohm diff DisplayPort A Lane3 2 SG
67 DP_A_L3# O Diff 90Ohm diff 2 SF
68 TH_ALERT# O OD N/A Thermal interrupt request. Connect to EC 5 SB
69 DP_A_AUX I/O Diff/OD 90Ohm diff DisplayPort A auxiliary channel/DDC. When using an Expansion Bay Module that uses two PCIe ports, it will switch to the 2nd PCIe clock 7 SK
70 DP_A_AUX# I/O Diff/OD 90Ohm diff 7 SJ
71 PNL_PWR_EN O CMOS N/A 3.3V Internal panel power enable. Connect to internal display 5 SK
72 PNL_BL_PWM O CMOS N/A 3.3V Internal panel PWM brightness control. Connect to internal display 4 SK
73 ID1 O OD N/A Connect to EC ADC with 100K pull-up to identify if the power connector is well connected 2 SL
74 GPIO3_EC I/O CMOS N/A 3.3V Connect to EC GPIO 7 SL

Power

TODO