cad/yosys: update 0.35 → 0.36

Reported by: portscout
freebsd · Dec 6, 2023 · 124e43e · 124e43e
1 parent d57a48f
commit 124e43e
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Showing 3 changed files with 34 additions and 20 deletions.
diff --git a/cad/yosys/Makefile b/cad/yosys/Makefile
@@ -1,6 +1,6 @@
 PORTNAME=	yosys
 DISTVERSIONPREFIX=	yosys-
-DISTVERSION=	0.35
+DISTVERSION=	0.36
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org

diff --git a/cad/yosys/distinfo b/cad/yosys/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1699426658
-SHA256 (YosysHQ-yosys-yosys-0.35_GH0.tar.gz) = a00643cf4cf83701bfa2b358066eb9d360393d30e8f5a8e65f619ab1fd10474a
-SIZE (YosysHQ-yosys-yosys-0.35_GH0.tar.gz) = 2614018
+TIMESTAMP = 1701840331
+SHA256 (YosysHQ-yosys-yosys-0.36_GH0.tar.gz) = d69beedcb76db80681c2a0f445046311f3ba16716d5d0c3c5034dabcb6bd9b23
+SIZE (YosysHQ-yosys-yosys-0.36_GH0.tar.gz) = 2688211
diff --git a/cad/yosys/pkg-plist b/cad/yosys/pkg-plist
@@ -20,6 +20,7 @@ bin/yosys-witness
 %%DATADIR%%/cells.lib
 %%DATADIR%%/cmp2lcu.v
 %%DATADIR%%/cmp2lut.v
+%%DATADIR%%/cmp2softlogic.v
 %%DATADIR%%/coolrunner2/cells_counter_map.v
 %%DATADIR%%/coolrunner2/cells_latch.v
 %%DATADIR%%/coolrunner2/cells_sim.v
@@ -94,12 +95,12 @@ bin/yosys-witness
 %%DATADIR%%/ice40/latches_map.v
 %%DATADIR%%/ice40/spram.txt
 %%DATADIR%%/ice40/spram_map.v
-%%DATADIR%%/include/backends/cxxrtl/cxxrtl.h
-%%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.cc
-%%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.h
-%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd.h
-%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
-%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.h
+%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
+%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
+%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
+%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
+%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
 %%DATADIR%%/include/backends/rtlil/rtlil_backend.h
 %%DATADIR%%/include/frontends/ast/ast.h
 %%DATADIR%%/include/frontends/ast/ast_binding.h
@@ -211,16 +212,29 @@ bin/yosys-witness
 %%DATADIR%%/pmux2mux.v
 %%DATADIR%%/python3/smtio.py
 %%DATADIR%%/python3/ywio.py
-%%DATADIR%%/quicklogic/abc9_map.v
-%%DATADIR%%/quicklogic/abc9_model.v
-%%DATADIR%%/quicklogic/abc9_unmap.v
-%%DATADIR%%/quicklogic/cells_sim.v
-%%DATADIR%%/quicklogic/lut_sim.v
-%%DATADIR%%/quicklogic/pp3_cells_map.v
-%%DATADIR%%/quicklogic/pp3_cells_sim.v
-%%DATADIR%%/quicklogic/pp3_ffs_map.v
-%%DATADIR%%/quicklogic/pp3_latches_map.v
-%%DATADIR%%/quicklogic/pp3_lut_map.v
+%%DATADIR%%/quicklogic/common/cells_sim.v
+%%DATADIR%%/quicklogic/pp3/abc9_map.v
+%%DATADIR%%/quicklogic/pp3/abc9_model.v
+%%DATADIR%%/quicklogic/pp3/abc9_unmap.v
+%%DATADIR%%/quicklogic/pp3/cells_map.v
+%%DATADIR%%/quicklogic/pp3/cells_sim.v
+%%DATADIR%%/quicklogic/pp3/ffs_map.v
+%%DATADIR%%/quicklogic/pp3/latches_map.v
+%%DATADIR%%/quicklogic/pp3/lut_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/arith_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/bram_types_sim.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/brams_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/brams_sim.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/cells_sim.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/dsp_final_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/dsp_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/dsp_sim.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/ffs_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/libmap_brams.txt
+%%DATADIR%%/quicklogic/qlf_k6n10f/libmap_brams_map.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/sram1024x18_mem.v
+%%DATADIR%%/quicklogic/qlf_k6n10f/ufifo_ctl.v
 %%DATADIR%%/sf2/arith_map.v
 %%DATADIR%%/sf2/cells_map.v
 %%DATADIR%%/sf2/cells_sim.v