arm64: dts: imx8: gpu0: move into a separate ss dtsi

move gpu0 changes into a separate ss dtsi Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Freescale · Dec 12, 2022 · d0964b3 · d0964b3
1 parent 7e9dffb
commit d0964b3
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Showing 2 changed files with 37 additions and 29 deletions.
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-gpu0.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ *	Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/firmware/imx/rsrc.h>
+
+gpu_subsys: bus@53100000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x53100000 0x0 0x53100000 0x40000>;
+
+	gpu_3d0: gpu@53100000 {
+		compatible = "fsl,imx8-gpu";
+		reg = <0x53100000 0x40000>;
+		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+			 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+		clock-names = "core", "shader";
+		assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
+				  <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
+		assigned-clock-rates = <700000000>, <850000000>;
+		power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
+		status = "disabled";
+	};
+
+	imx8_gpu_ss: imx8_gpu_ss {
+		compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
+		cores = <&gpu_3d0>;
+		reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>;
+		reg-names = "phys_baseaddr", "contiguous_mem";
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -319,35 +319,6 @@
 		fsl,heap-id = <0>;
 	};
 
-	gpu_subsys: bus@53100000 {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges = <0x53100000 0x0 0x53100000 0x40000>;
-
-		gpu_3d0: gpu@53100000 {
-			compatible = "fsl,imx8-gpu";
-			reg = <0x53100000 0x40000>;
-			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
-				 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
-			clock-names = "core", "shader";
-			assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
-					  <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
-			assigned-clock-rates = <700000000>, <850000000>;
-			power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
-			status = "disabled";
-		};
-
-		imx8_gpu_ss: imx8_gpu_ss {
-			compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss";
-			cores = <&gpu_3d0>;
-			reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>;
-			reg-names = "phys_baseaddr", "contiguous_mem";
-			status = "disabled";
-		};
-	};
-
 	rpmsg: rpmsg{
 		compatible = "fsl,imx8qxp-rpmsg";
 		/* up to now, the following channels are used in imx rpmsg
@@ -366,6 +337,7 @@
 	/* sorted in register address */
 	#include "imx8-ss-img.dtsi"
 	#include "imx8-ss-cm40.dtsi"
+	#include "imx8-ss-gpu0.dtsi"
 	#include "imx8-ss-vpu.dtsi"
 	#include "imx8-ss-dc.dtsi"
 	#include "imx8-ss-lvds.dtsi"