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Part pipeline: Extra tests for part-pipeline scheme
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Add tests with -enable-part-pipeline option.
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@piotrAMD
piotrAMD committed Apr 4, 2022
1 parent df8082f commit 478469b
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99 changes: 68 additions & 31 deletions llpc/test/shaderdb/general/PipelineTess_TestInOutPacking.pipe
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@@ -1,35 +1,72 @@
; BEGIN_SHADERTEST
; RUN: amdllpc -spvgen-dir=%spvgendir% -v %gfxip %s | FileCheck -check-prefix=SHADERTEST %s
; SHADERTEST-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 40
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 1
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 2
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 3
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 8
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 12
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 16
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 20
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 4
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 24
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 28
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 32
; SHADERTEST: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 36
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 4
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 10
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 12
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 8
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 52
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 96
; SHADERTEST: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 24
; SHADERTEST: call void @llvm.amdgcn.exp.f32(i32 {{.*}}32, i32 {{.*}}15, float %{{[0-9]*}}, float %{{[0-9]*}}, float %{{[0-9]*}}, float %{{[0-9]*}}, i1 {{.*}}false, i1 {{.*}}false)
; SHADERTEST: call void @llvm.amdgcn.exp.f32(i32 {{.*}}33, i32 {{.*}}3, float %{{[0-9]*}}, float %{{[0-9]*}}, float undef, float undef, i1 {{.*}}false, i1 {{.*}}false)
; SHADERTEST: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 1, i32 %PrimMask)
; SHADERTEST: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 2, i32 immarg 0, i32 %PrimMask)
; SHADERTEST: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 3, i32 immarg 0, i32 %PrimMask)
; SHADERTEST: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 0, i32 immarg 1, i32 %PrimMask)
; SHADERTEST: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 0, i32 immarg 0, i32 %PrimMask)
; SHADERTEST: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 0, i32 %PrimMask)
; SHADERTEST: AMDLLPC SUCCESS
; RUN: amdllpc -enable-part-pipeline=0 -spvgen-dir=%spvgendir% -v %gfxip %s | FileCheck -check-prefix=SHADERTEST_PP0 %s
; SHADERTEST_PP0-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 40
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 1
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 2
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 3
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 8
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 12
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 16
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 20
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 4
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 24
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 28
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 32
; SHADERTEST_PP0: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 36
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 4
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 10
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 12
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 8
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 52
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 96
; SHADERTEST_PP0: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 24
; SHADERTEST_PP0: call void @llvm.amdgcn.exp.f32(i32 {{.*}}32, i32 {{.*}}15, float %{{[0-9]*}}, float %{{[0-9]*}}, float %{{[0-9]*}}, float %{{[0-9]*}}, i1 {{.*}}false, i1 {{.*}}false)
; SHADERTEST_PP0: call void @llvm.amdgcn.exp.f32(i32 {{.*}}33, i32 {{.*}}3, float %{{[0-9]*}}, float %{{[0-9]*}}, float undef, float undef, i1 {{.*}}false, i1 {{.*}}false)
; SHADERTEST_PP0: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 1, i32 %PrimMask)
; SHADERTEST_PP0: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 2, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP0: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 3, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP0: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 0, i32 immarg 1, i32 %PrimMask)
; SHADERTEST_PP0: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 0, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP0: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP0: AMDLLPC SUCCESS
; END_SHADERTEST

; BEGIN_SHADERTEST
; RUN: amdllpc -enable-part-pipeline=1 -spvgen-dir=%spvgendir% -v %gfxip %s | FileCheck -check-prefix=SHADERTEST_PP1 %s
; Fragment shader part-pipeline:
; SHADERTEST_PP1-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 1, i32 %PrimMask)
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 2, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 3, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 0, i32 immarg 1, i32 %PrimMask)
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 0, i32 immarg 0, i32 %PrimMask)
; SHADERTEST_PP1: call float @llvm.amdgcn.interp.p1(float %{{[^,]*}}, i32 immarg 1, i32 immarg 0, i32 %PrimMask)
; Pre-rasterization part-pipeline:
; SHADERTEST_PP1-LABEL: {{^// LLPC}} pipeline patching results
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 40
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 1
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 2
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 3
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 8
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 12
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 16
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 20
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 4
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 24
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 28
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 32
; SHADERTEST_PP1: %{{[0-9]*}} = add i32 %{{[0-9]*}}, 36
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 4
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 10
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 12
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 8
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 52
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 96
; SHADERTEST_PP1: %{{[0-9]*}} = add nuw nsw i32 %{{[0-9]*}}, 24
; SHADERTEST_PP1: call void @llvm.amdgcn.exp.f32(i32 {{.*}}32, i32 {{.*}}15, float %{{[0-9]*}}, float %{{[0-9]*}}, float %{{[0-9]*}}, float %{{[0-9]*}}, i1 {{.*}}false, i1 {{.*}}false)
; SHADERTEST_PP1: call void @llvm.amdgcn.exp.f32(i32 {{.*}}33, i32 {{.*}}3, float %{{[0-9]*}}, float %{{[0-9]*}}, float undef, float undef, i1 {{.*}}false, i1 {{.*}}false)
; SHADERTEST_PP1: AMDLLPC SUCCESS
; END_SHADERTEST

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61 changes: 42 additions & 19 deletions llpc/test/shaderdb/general/PipelineVsFs_FsWithData.pipe
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Expand Up @@ -22,25 +22,48 @@
; END_SHADERTEST

; BEGIN_SHADERTEST
; RUN: amdllpc -spvgen-dir=%spvgendir% -o %t.elf %gfxip %s && llvm-objdump --arch=amdgcn --disassemble-zeroes --mcpu=gfx900 -d -j .text -j .rodata -r %t.elf | FileCheck -check-prefix=SHADERTEST2 %s
; SHADERTEST2-LABEL: <_amdgpu_ps_main>:
; SHADERTEST2: s_add_u32 {{s[0-9]*}}, {{s[0-9]*}}, 4
; SHADERTEST2-NEXT: R_AMDGPU_REL32_LO .rodata
; SHADERTEST2-NEXT: s_addc_u32 {{s[0-9]*}}, {{s[0-9]*}}, {{4|12}}
; SHADERTEST2-NEXT: R_AMDGPU_REL32_HI .rodata
; SHADERTEST2-LABEL: <__llpc_global_proxy_{{.*}}>:
; SHADERTEST2-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2-NEXT: {{[0-9]*}}: 3F800000
; RUN: amdllpc -enable-part-pipeline=0 -spvgen-dir=%spvgendir% -o %t.elf %gfxip %s && llvm-objdump --arch=amdgcn --disassemble-zeroes --mcpu=gfx900 -d -j .text -j .rodata -r %t.elf | FileCheck -check-prefix=SHADERTEST2_PP0 %s
; SHADERTEST2_PP0-LABEL: <_amdgpu_ps_main>:
; SHADERTEST2_PP0: s_add_u32 {{s[0-9]*}}, {{s[0-9]*}}, 4
; SHADERTEST2_PP0-NEXT: R_AMDGPU_REL32_LO .rodata
; SHADERTEST2_PP0-NEXT: s_addc_u32 {{s[0-9]*}}, {{s[0-9]*}}, {{4|12}}
; SHADERTEST2_PP0-NEXT: R_AMDGPU_REL32_HI .rodata
; SHADERTEST2_PP0-LABEL: <__llpc_global_proxy_{{.*}}>:
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP0-NEXT: {{[0-9]*}}: 3F800000
; END_SHADERTEST


; BEGIN_SHADERTEST
; RUN: amdllpc -enable-part-pipeline=1 -spvgen-dir=%spvgendir% -o %t.elf %gfxip %s && llvm-objdump --arch=amdgcn --disassemble-zeroes --mcpu=gfx900 -d -j .text -j .rodata -r %t.elf | FileCheck -check-prefix=SHADERTEST2_PP1 %s
; SHADERTEST2_PP1-LABEL: <_amdgpu_ps_main>:
; SHADERTEST2_PP1: s_add_u32 {{s[0-9]*}}, {{s[0-9]*}}, 4
; SHADERTEST2_PP1-NEXT: R_AMDGPU_REL32_LO [[fs_data_sym:[.a-z]*]]
; SHADERTEST2_PP1-NEXT: s_addc_u32 {{s[0-9]*}}, {{s[0-9]*}}, {{4|12}}
; SHADERTEST2_PP1-NEXT: R_AMDGPU_REL32_HI [[fs_data_sym]]
; SHADERTEST2_PP1: 0000000000000000 <[[fs_data_sym]]>:
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 00000000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 3F800000
; SHADERTEST2_PP1-NEXT: {{[0-9]*}}: 3F800000
; END_SHADERTEST

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