A MIPS assembly simulator is implemented with support for multicore processors. There are N cores and to handle the DRAM requests, a Memory Request Manager is designed.
- Compile the file
code.cpp
using the command-g++ -O3 code.cpp -o out
- Run the command-
Where,
./out N M R C D
N
is the number of cores.M
is the maximum number of clock cycles available for execution.R
andC
are row access delay and column access delay respectively.D
is a single bit to show the execution details or not.
The code will ask the names of the text files containing the instructions for each core. This process will happen N times.
Number of instructions executed for each core and total instructions executed are shown. Instructions per cycle (IPC) can easily be calculated using these values.
Some sample testcases are also present to try out the simulator.
- Gaurav Jain - 2019CS10349
- T Abishek - 2019CS10407
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