1.Use the given RTL and simulation sources
2.Run the simulation
3.Generate the Constarints File
4.Since clock is not defined for simulation it cannot have any reference to report the timing
5.Timing Constraints
6.This is power consumed by the FPGA to implement the design
---------------------------------------------------------------------------------------------------------
Ran the VTR command with Earch file and Berkeley Logic Interchange Format (Blif) file https://course.ece.cmu.edu/~ee760/760docs/blif.pdf
This is the command with the display ON.
1..net file contains the netlist 2..place gives the placement 3..route the routing that has done 4.packing pin report will the pin utilisation 5.report_timing_setup will give the timing analysis
- Since the timing constraints is not provided the this will not be a valid analysis
After the passing on the Blif file the
