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dhd_pcie_linux.c
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dhd_pcie_linux.c
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/*
* Linux DHD Bus Module for PCIE
*
* Copyright (C) 2022, Broadcom.
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
*
* <<Broadcom-WL-IPTag/Open:>>
*
* $Id$
*/
/* include files */
#include <typedefs.h>
#include <bcmutils.h>
#include <bcmdevs.h>
#include <bcmdevs_legacy.h> /* need to still support chips no longer in trunk firmware */
#include <siutils.h>
#include <hndsoc.h>
#include <hndpmu.h>
#include <sbchipc.h>
#if defined(DHD_DEBUG)
#include <hnd_armtrap.h>
#include <hnd_cons.h>
#endif /* defined(DHD_DEBUG) */
#include <dngl_stats.h>
#include <pcie_core.h>
#include <dhd.h>
#include <dhd_bus.h>
#include <dhd_proto.h>
#include <dhd_dbg.h>
#include <dhdioctl.h>
#include <bcmmsgbuf.h>
#include <pcicfg.h>
#include <dhd_pcie.h>
#include <dhd_linux.h>
#ifdef CONFIG_ARCH_MSM
#if IS_ENABLED(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996)
#include <linux/msm_pcie.h>
#else
#include <mach/msm_pcie.h>
#endif /* CONFIG_PCI_MSM */
#endif /* CONFIG_ARCH_MSM */
#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
#include <linux/pm_runtime.h>
#ifndef AUTO_SUSPEND_TIMEOUT
#define AUTO_SUSPEND_TIMEOUT 1000
#endif /* AUTO_SUSPEND_TIMEOUT */
#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
#ifdef DHD_PCIE_RUNTIMEPM
#define RPM_WAKE_UP_TIMEOUT 10000 /* ms */
#endif /* DHD_PCIE_RUNTIMEPM */
#include <linux/irq.h>
#ifdef USE_SMMU_ARCH_MSM
#include <asm/dma-iommu.h>
#include <linux/iommu.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#endif /* USE_SMMU_ARCH_MSM */
#ifdef PCIE_OOB
#include "ftdi_sio_external.h"
#endif /* PCIE_OOB */
#if defined(WL_CFG80211)
#include <wl_cfg80211.h>
#endif /* WL_CFG80211 */
#include <dhd_plat.h>
#define PCI_CFG_RETRY 10 /* PR15065: retry count for pci cfg accesses */
#define OS_HANDLE_MAGIC 0x1234abcd /* Magic # to recognize osh */
#define BCM_MEM_FILENAME_LEN 24 /* Mem. filename length */
#ifdef PCIE_OOB
#define HOST_WAKE 4 /* GPIO_0 (HOST_WAKE) - Output from WLAN */
#define DEVICE_WAKE 5 /* GPIO_1 (DEVICE_WAKE) - Input to WLAN */
#define BIT_WL_REG_ON 6
#define BIT_BT_REG_ON 7
int gpio_handle_val = 0;
unsigned char gpio_port = 0;
unsigned char gpio_direction = 0;
#define OOB_PORT "ttyUSB0"
#endif /* PCIE_OOB */
#ifndef BCMPCI_DEV_ID
#define BCMPCI_DEV_ID PCI_ANY_ID
#endif
#ifdef FORCE_TPOWERON
extern uint32 tpoweron_scale;
#endif /* FORCE_TPOWERON */
/* user defined data structures */
typedef bool (*dhdpcie_cb_fn_t)(void *);
typedef struct dhdpcie_info
{
dhd_bus_t *bus;
osl_t *osh;
struct pci_dev *dev; /* pci device handle */
volatile char *regs; /* pci device memory va */
volatile char *tcm; /* pci device memory va */
uint32 bar1_size; /* pci device memory size */
struct pcos_info *pcos_info;
uint16 last_intrstatus; /* to cache intrstatus */
int irq;
char pciname[32];
struct pci_saved_state* default_state;
struct pci_saved_state* state;
#ifdef BCMPCIE_OOB_HOST_WAKE
void *os_cxt; /* Pointer to per-OS private data */
#endif /* BCMPCIE_OOB_HOST_WAKE */
#ifdef DHD_WAKE_STATUS
spinlock_t pkt_wake_lock;
unsigned int total_wake_count;
int pkt_wake;
int wake_irq;
int pkt_wake_dump;
#endif /* DHD_WAKE_STATUS */
#ifdef USE_SMMU_ARCH_MSM
void *smmu_cxt;
#endif /* USE_SMMU_ARCH_MSM */
} dhdpcie_info_t;
struct pcos_info {
dhdpcie_info_t *pc;
spinlock_t lock;
wait_queue_head_t intr_wait_queue;
timer_list_compat_t tuning_timer;
int tuning_timer_exp;
atomic_t timer_enab;
struct tasklet_struct tuning_tasklet;
};
#ifdef BCMPCIE_OOB_HOST_WAKE
typedef struct dhdpcie_os_info {
int oob_irq_num; /* valid when hardware or software oob in use */
unsigned long oob_irq_flags; /* valid when hardware or software oob in use */
bool oob_irq_registered;
bool oob_irq_enabled;
bool oob_irq_wake_enabled;
spinlock_t oob_irq_spinlock;
void *dev; /* handle to the underlying device */
} dhdpcie_os_info_t;
static irqreturn_t wlan_oob_irq(int irq, void *data);
#ifdef CUSTOMER_HW2
extern struct brcm_pcie_wake brcm_pcie_wake;
#endif /* CUSTOMER_HW2 */
#endif /* BCMPCIE_OOB_HOST_WAKE */
#ifdef USE_SMMU_ARCH_MSM
typedef struct dhdpcie_smmu_info {
struct dma_iommu_mapping *smmu_mapping;
dma_addr_t smmu_iova_start;
size_t smmu_iova_len;
} dhdpcie_smmu_info_t;
#endif /* USE_SMMU_ARCH_MSM */
/* function declarations */
static int __devinit
dhdpcie_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
static void __devexit dhdpcie_pci_remove(struct pci_dev *pdev);
static void __devexit dhdpcie_pci_shutdown(struct pci_dev *pdev);
static void __devexit dhdpcie_pci_stop(struct pci_dev *pdev);
static int dhdpcie_init(struct pci_dev *pdev);
static irqreturn_t dhdpcie_isr(int irq, void *arg);
/* OS Routine functions for PCI suspend/resume */
#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
static int dhdpcie_set_suspend_resume(struct pci_dev *dev, bool state, bool byint);
#else
static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state);
#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
static int dhdpcie_resume_host_dev(dhd_bus_t *bus);
static int dhdpcie_suspend_host_dev(dhd_bus_t *bus);
static int dhdpcie_resume_dev(struct pci_dev *dev);
static int dhdpcie_suspend_dev(struct pci_dev *dev);
#ifdef DHD_PCIE_RUNTIMEPM
static int dhdpcie_pm_suspend(struct device *dev);
static int dhdpcie_pm_prepare(struct device *dev);
static int dhdpcie_pm_resume(struct device *dev);
static void dhdpcie_pm_complete(struct device *dev);
#else
#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
static int dhdpcie_pm_system_suspend_noirq(struct device * dev);
static int dhdpcie_pm_system_resume_noirq(struct device * dev);
#else
static int dhdpcie_pci_suspend(struct device * dev);
static int dhdpcie_pci_resume(struct device * dev);
static int dhdpcie_pci_resume_early(struct device * dev);
#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
#endif /* DHD_PCIE_RUNTIMEPM */
#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
static int dhdpcie_pm_runtime_suspend(struct device * dev);
static int dhdpcie_pm_runtime_resume(struct device * dev);
static int dhdpcie_pm_system_suspend_noirq(struct device * dev);
static int dhdpcie_pm_system_resume_noirq(struct device * dev);
#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
static void dhdpcie_config_save_restore_coherent(dhd_bus_t *bus, bool state);
uint32
dhdpcie_access_cap(struct pci_dev *pdev, int cap, uint offset, bool is_ext, bool is_write,
uint32 writeval);
static struct pci_device_id dhdpcie_pci_devid[] __devinitdata = {
{ vendor: VENDOR_BROADCOM,
device: BCMPCI_DEV_ID,
subvendor: PCI_ANY_ID,
subdevice: PCI_ANY_ID,
class: PCI_CLASS_NETWORK_OTHER << 8,
class_mask: 0xffff00,
driver_data: 0,
},
#if (BCMPCI_DEV_ID != PCI_ANY_ID) && defined(BCMPCI_NOOTP_DEV_ID)
{ vendor: VENDOR_BROADCOM,
device: BCMPCI_NOOTP_DEV_ID,
subvendor: PCI_ANY_ID,
subdevice: PCI_ANY_ID,
class: PCI_CLASS_NETWORK_OTHER << 8,
class_mask: 0xffff00,
driver_data: 0,
},
#endif /* BCMPCI_DEV_ID != PCI_ANY_ID && BCMPCI_NOOTP_DEV_ID */
{ 0, 0, 0, 0, 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, dhdpcie_pci_devid);
/* Power Management Hooks */
#ifdef DHD_PCIE_RUNTIMEPM
static const struct dev_pm_ops dhd_pcie_pm_ops = {
.prepare = dhdpcie_pm_prepare,
.suspend = dhdpcie_pm_suspend,
.resume = dhdpcie_pm_resume,
.complete = dhdpcie_pm_complete,
};
#elif defined(DHD_PCIE_NATIVE_RUNTIMEPM)
static const struct dev_pm_ops dhdpcie_pm_ops = {
SET_RUNTIME_PM_OPS(dhdpcie_pm_runtime_suspend, dhdpcie_pm_runtime_resume, NULL)
.suspend_noirq = dhdpcie_pm_system_suspend_noirq,
.resume_noirq = dhdpcie_pm_system_resume_noirq
};
#else
/* for linux platforms */
static const struct dev_pm_ops dhd_pcie_pm_ops = {
.suspend = dhdpcie_pci_suspend,
.resume = dhdpcie_pci_resume,
.resume_early = dhdpcie_pci_resume_early,
};
#endif /* DHD_PCIE_RUNTIMEPM */
static struct pci_driver dhdpcie_driver = {
node: {&dhdpcie_driver.node, &dhdpcie_driver.node},
name: "pcieh",
id_table: dhdpcie_pci_devid,
probe: dhdpcie_pci_probe,
remove: dhdpcie_pci_remove,
.driver.pm = &dhd_pcie_pm_ops,
shutdown: dhdpcie_pci_shutdown,
};
int dhdpcie_init_succeeded = FALSE;
#if defined(CUSTOMER_HW4_DEBUG)
char dhd_suspend_resume_time_str[DEBUG_DUMP_TIME_BUF_LEN];
#endif /* CUSTOMER_HW4_DEBUG */
#ifdef USE_SMMU_ARCH_MSM
static int dhdpcie_smmu_init(struct pci_dev *pdev, void *smmu_cxt)
{
struct dma_iommu_mapping *mapping;
struct device_node *root_node = NULL;
dhdpcie_smmu_info_t *smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
int smmu_iova_address[2];
char *wlan_node = "android,bcmdhd_wlan";
char *wlan_smmu_node = "wlan-smmu-iova-address";
int atomic_ctx = 1;
int s1_bypass = 1;
int ret = 0;
DHD_ERROR(("%s: SMMU initialize\n", __FUNCTION__));
root_node = of_find_compatible_node(NULL, NULL, wlan_node);
if (!root_node) {
WARN(1, "failed to get device node of BRCM WLAN\n");
return -ENODEV;
}
if (of_property_read_u32_array(root_node, wlan_smmu_node,
smmu_iova_address, 2) == 0) {
DHD_ERROR(("%s : get SMMU start address 0x%x, size 0x%x\n",
__FUNCTION__, smmu_iova_address[0], smmu_iova_address[1]));
smmu_info->smmu_iova_start = smmu_iova_address[0];
smmu_info->smmu_iova_len = smmu_iova_address[1];
} else {
DHD_CONS_ONLY(("%s : can't get smmu iova address property\n",
__FUNCTION__));
return -ENODEV;
}
if (smmu_info->smmu_iova_len <= 0) {
DHD_ERROR(("%s: Invalid smmu iova len %d\n",
__FUNCTION__, (int)smmu_info->smmu_iova_len));
return -EINVAL;
}
DHD_ERROR(("%s : SMMU init start\n", __FUNCTION__));
if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) ||
pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
DHD_ERROR(("%s: DMA set 64bit mask failed.\n", __FUNCTION__));
return -EINVAL;
}
mapping = arm_iommu_create_mapping(&platform_bus_type,
smmu_info->smmu_iova_start, smmu_info->smmu_iova_len);
if (IS_ERR(mapping)) {
DHD_ERROR(("%s: create mapping failed, err = %d\n",
__FUNCTION__, ret));
ret = PTR_ERR(mapping);
goto map_fail;
}
ret = iommu_domain_set_attr(mapping->domain,
DOMAIN_ATTR_ATOMIC, &atomic_ctx);
if (ret) {
DHD_ERROR(("%s: set atomic_ctx attribute failed, err = %d\n",
__FUNCTION__, ret));
goto set_attr_fail;
}
ret = iommu_domain_set_attr(mapping->domain,
DOMAIN_ATTR_S1_BYPASS, &s1_bypass);
if (ret < 0) {
DHD_ERROR(("%s: set s1_bypass attribute failed, err = %d\n",
__FUNCTION__, ret));
goto set_attr_fail;
}
ret = arm_iommu_attach_device(&pdev->dev, mapping);
if (ret) {
DHD_ERROR(("%s: attach device failed, err = %d\n",
__FUNCTION__, ret));
goto attach_fail;
}
smmu_info->smmu_mapping = mapping;
return ret;
attach_fail:
set_attr_fail:
arm_iommu_release_mapping(mapping);
map_fail:
return ret;
}
static void dhdpcie_smmu_remove(struct pci_dev *pdev, void *smmu_cxt)
{
dhdpcie_smmu_info_t *smmu_info;
if (!smmu_cxt) {
return;
}
smmu_info = (dhdpcie_smmu_info_t *)smmu_cxt;
if (smmu_info->smmu_mapping) {
arm_iommu_detach_device(&pdev->dev);
arm_iommu_release_mapping(smmu_info->smmu_mapping);
smmu_info->smmu_mapping = NULL;
}
}
#endif /* USE_SMMU_ARCH_MSM */
#ifdef FORCE_TPOWERON
static void
dhd_bus_get_tpoweron(dhd_bus_t *bus)
{
uint32 tpoweron_rc;
uint32 tpoweron_ep;
tpoweron_rc = dhdpcie_rc_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, FALSE, 0);
tpoweron_ep = dhdpcie_ep_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, FALSE, 0);
DHD_ERROR(("%s: tpoweron_rc:0x%x tpoweron_ep:0x%x\n",
__FUNCTION__, tpoweron_rc, tpoweron_ep));
}
static void
dhd_bus_set_tpoweron(dhd_bus_t *bus, uint16 tpoweron)
{
dhd_bus_get_tpoweron(bus);
/* Set the tpoweron */
DHD_ERROR(("%s tpoweron: 0x%x\n", __FUNCTION__, tpoweron));
dhdpcie_rc_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, TRUE, tpoweron);
dhdpcie_ep_access_cap(bus, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL2_OFFSET, TRUE, TRUE, tpoweron);
dhd_bus_get_tpoweron(bus);
}
static bool
dhdpcie_chip_req_forced_tpoweron(dhd_bus_t *bus)
{
/*
* On Fire's reference platform, coming out of L1.2,
* there is a constant delay of 45us between CLKREQ# and stable REFCLK
* Due to this delay, with tPowerOn < 50
* there is a chance of the refclk sense to trigger on noise.
*
* Which ever chip needs forced tPowerOn of 50us should be listed below.
*/
if (si_chipid(bus->sih) == BCM4377_CHIP_ID) {
return TRUE;
}
return FALSE;
}
#endif /* FORCE_TPOWERON */
static bool
dhd_bus_aspm_enable_dev(dhd_bus_t *bus, struct pci_dev *dev, bool enable)
{
uint32 linkctrl_before;
uint32 linkctrl_after = 0;
uint8 linkctrl_aspm;
char *device;
device = (dev == bus->dev) ? "EP" : "RC";
linkctrl_before = dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
FALSE, FALSE, 0);
linkctrl_aspm = (linkctrl_before & PCIE_ASPM_CTRL_MASK);
if (enable) {
if (linkctrl_aspm == PCIE_ASPM_L1_ENAB) {
DHD_ERROR(("%s: %s already enabled linkctrl: 0x%x\n",
__FUNCTION__, device, linkctrl_before));
return FALSE;
}
/* Enable only L1 ASPM (bit 1) */
dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET, FALSE,
TRUE, (linkctrl_before | PCIE_ASPM_L1_ENAB));
} else {
if (linkctrl_aspm == 0) {
DHD_ERROR(("%s: %s already disabled linkctrl: 0x%x\n",
__FUNCTION__, device, linkctrl_before));
return FALSE;
}
/* Disable complete ASPM (bit 1 and bit 0) */
dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET, FALSE,
TRUE, (linkctrl_before & (~PCIE_ASPM_ENAB)));
}
linkctrl_after = dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
FALSE, FALSE, 0);
DHD_ERROR(("%s: %s %s, linkctrl_before: 0x%x linkctrl_after: 0x%x\n",
__FUNCTION__, device, (enable ? "ENABLE " : "DISABLE"),
linkctrl_before, linkctrl_after));
return TRUE;
}
static bool
dhd_bus_is_aspm_enab_dev(dhd_bus_t *bus, struct pci_dev *dev)
{
uint32 linkctrl = dhdpcie_access_cap(dev, PCIE_CAP_ID_EXP,
PCIE_CAP_LINKCTRL_OFFSET, FALSE, FALSE, 0);
DHD_INFO(("%s: %s: linkctrl:0x%x\n",
__FUNCTION__, (dev == bus->dev) ? "EP" : "RC", linkctrl));
return ((linkctrl & PCIE_ASPM_CTRL_MASK) == PCIE_ASPM_L1_ENAB);
}
bool
dhd_bus_is_aspm_enab_rc_ep(dhd_bus_t *bus)
{
uint32 rc_aspm_enab;
uint32 ep_aspm_enab;
rc_aspm_enab = dhd_bus_is_aspm_enab_dev(bus, bus->rc_dev);
ep_aspm_enab = dhd_bus_is_aspm_enab_dev(bus, bus->dev);
return (rc_aspm_enab && ep_aspm_enab);
}
static bool
dhd_bus_is_rc_ep_aspm_capable(dhd_bus_t *bus)
{
uint32 rc_aspm_cap;
uint32 ep_aspm_cap;
/* RC ASPM capability */
rc_aspm_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
FALSE, FALSE, 0);
if (rc_aspm_cap == BCME_ERROR) {
DHD_ERROR(("%s RC is not ASPM capable\n", __FUNCTION__));
return FALSE;
}
/* EP ASPM capability */
ep_aspm_cap = dhdpcie_access_cap(bus->dev, PCIE_CAP_ID_EXP, PCIE_CAP_LINKCTRL_OFFSET,
FALSE, FALSE, 0);
if (ep_aspm_cap == BCME_ERROR) {
DHD_ERROR(("%s EP is not ASPM capable\n", __FUNCTION__));
return FALSE;
}
return TRUE;
}
bool
dhd_bus_aspm_enable_rc_ep(dhd_bus_t *bus, bool enable)
{
bool ret;
if (!bus->rc_ep_aspm_cap) {
DHD_ERROR(("%s: NOT ASPM CAPABLE rc_ep_aspm_cap: %d\n",
__FUNCTION__, bus->rc_ep_aspm_cap));
return FALSE;
}
if (enable) {
/* Enable only L1 ASPM first RC then EP */
ret = dhd_bus_aspm_enable_dev(bus, bus->rc_dev, enable);
ret = dhd_bus_aspm_enable_dev(bus, bus->dev, enable);
} else {
/* Disable complete ASPM first EP then RC */
ret = dhd_bus_aspm_enable_dev(bus, bus->dev, enable);
ret = dhd_bus_aspm_enable_dev(bus, bus->rc_dev, enable);
}
return ret;
}
static bool
dhd_bus_is_l1ss_enab_dev(dhd_bus_t *bus, struct pci_dev *dev)
{
uint32 l1ssctrl;
/* Extendend Capacility Reg */
l1ssctrl = dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
DHD_INFO(("%s: %s: l1ssctrl:0x%x\n",
__FUNCTION__, (dev == bus->dev) ? "EP" : "RC", l1ssctrl));
return ((l1ssctrl & PCIE_EXT_L1SS_MASK) == PCIE_EXT_L1SS_ENAB);
}
bool
dhd_bus_is_l1ss_enab_rc_ep(dhd_bus_t *bus)
{
uint32 rc_l1ss_enab;
uint32 ep_l1ss_enab;
rc_l1ss_enab = dhd_bus_is_l1ss_enab_dev(bus, bus->rc_dev);
ep_l1ss_enab = dhd_bus_is_l1ss_enab_dev(bus, bus->dev);
return (rc_l1ss_enab && ep_l1ss_enab);
}
static void
dhd_bus_l1ss_enable_dev(dhd_bus_t *bus, struct pci_dev *dev, bool enable)
{
uint32 l1ssctrl_before;
uint32 l1ssctrl_after = 0;
uint8 l1ss_ep;
char *device;
device = (dev == bus->dev) ? "EP" : "RC";
/* Extendend Capacility Reg */
l1ssctrl_before = dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
l1ss_ep = (l1ssctrl_before & PCIE_EXT_L1SS_MASK);
if (enable) {
if (l1ss_ep == PCIE_EXT_L1SS_ENAB) {
DHD_ERROR(("%s: %s already enabled, l1ssctrl: 0x%x\n",
__FUNCTION__, device, l1ssctrl_before));
return;
}
dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS, PCIE_EXTCAP_L1SS_CONTROL_OFFSET,
TRUE, TRUE, (l1ssctrl_before | PCIE_EXT_L1SS_ENAB));
} else {
if (l1ss_ep == 0) {
DHD_ERROR(("%s: %s already disabled, l1ssctrl: 0x%x\n",
__FUNCTION__, device, l1ssctrl_before));
return;
}
dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS, PCIE_EXTCAP_L1SS_CONTROL_OFFSET,
TRUE, TRUE, (l1ssctrl_before & (~PCIE_EXT_L1SS_ENAB)));
}
l1ssctrl_after = dhdpcie_access_cap(dev, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
DHD_ERROR(("%s: %s %s, l1ssctrl_before: 0x%x l1ssctrl_after: 0x%x\n",
__FUNCTION__, device, (enable ? "ENABLE " : "DISABLE"),
l1ssctrl_before, l1ssctrl_after));
}
static bool
dhd_bus_is_rc_ep_l1ss_capable(dhd_bus_t *bus)
{
uint32 rc_l1ss_cap;
uint32 ep_l1ss_cap;
/* RC Extendend Capacility */
rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
if (rc_l1ss_cap == BCME_ERROR) {
DHD_ERROR(("%s RC is not l1ss capable\n", __FUNCTION__));
return FALSE;
}
/* EP Extendend Capacility */
ep_l1ss_cap = dhdpcie_access_cap(bus->dev, PCIE_EXTCAP_ID_L1SS,
PCIE_EXTCAP_L1SS_CONTROL_OFFSET, TRUE, FALSE, 0);
if (ep_l1ss_cap == BCME_ERROR) {
DHD_ERROR(("%s EP is not l1ss capable\n", __FUNCTION__));
return FALSE;
}
return TRUE;
}
void
dhd_bus_l1ss_enable_rc_ep(dhd_bus_t *bus, bool enable)
{
bool ret;
if ((!bus->rc_ep_aspm_cap) || (!bus->rc_ep_l1ss_cap)) {
DHD_ERROR(("%s: NOT L1SS CAPABLE rc_ep_aspm_cap: %d rc_ep_l1ss_cap: %d\n",
__FUNCTION__, bus->rc_ep_aspm_cap, bus->rc_ep_l1ss_cap));
return;
}
/* Disable ASPM of RC and EP */
ret = dhd_bus_aspm_enable_rc_ep(bus, FALSE);
if (enable) {
/* Enable RC then EP */
dhd_bus_l1ss_enable_dev(bus, bus->rc_dev, enable);
dhd_bus_l1ss_enable_dev(bus, bus->dev, enable);
} else {
/* Disable EP then RC */
dhd_bus_l1ss_enable_dev(bus, bus->dev, enable);
dhd_bus_l1ss_enable_dev(bus, bus->rc_dev, enable);
}
/* Enable ASPM of RC and EP only if this API disabled */
if (ret == TRUE) {
dhd_bus_aspm_enable_rc_ep(bus, TRUE);
}
}
void
dhd_bus_aer_config(dhd_bus_t *bus)
{
uint32 val;
DHD_ERROR_MEM(("%s: Configure AER registers for EP\n", __FUNCTION__));
val = dhdpcie_ep_access_cap(bus, PCIE_ADVERRREP_CAPID,
PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, FALSE, 0);
if (val != (uint32)-1) {
val &= ~CORR_ERR_AE;
dhdpcie_ep_access_cap(bus, PCIE_ADVERRREP_CAPID,
PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, TRUE, val);
} else {
DHD_ERROR(("%s: Invalid EP's PCIE_ADV_CORR_ERR_MASK: 0x%x\n",
__FUNCTION__, val));
}
DHD_ERROR_MEM(("%s: Configure AER registers for RC\n", __FUNCTION__));
val = dhdpcie_rc_access_cap(bus, PCIE_ADVERRREP_CAPID,
PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, FALSE, 0);
if (val != (uint32)-1) {
val &= ~CORR_ERR_AE;
dhdpcie_rc_access_cap(bus, PCIE_ADVERRREP_CAPID,
PCIE_ADV_CORR_ERR_MASK_OFFSET, TRUE, TRUE, val);
} else {
DHD_ERROR(("%s: Invalid RC's PCIE_ADV_CORR_ERR_MASK: 0x%x\n",
__FUNCTION__, val));
}
}
#ifdef DHD_PCIE_RUNTIMEPM
static int dhdpcie_pm_suspend(struct device *dev)
{
int ret = 0;
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
unsigned long flags;
if (pch) {
bus = pch->bus;
}
if (!bus) {
return ret;
}
DHD_GENERAL_LOCK(bus->dhd, flags);
if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
DHD_ERROR(("%s: Bus not IDLE!! dhd_bus_busy_state = 0x%x\n",
__FUNCTION__, bus->dhd->dhd_bus_busy_state));
DHD_GENERAL_UNLOCK(bus->dhd, flags);
return -EBUSY;
}
DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
if (bus->dhd->up)
ret = dhdpcie_set_suspend_resume(bus, TRUE);
DHD_GENERAL_LOCK(bus->dhd, flags);
DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
dhd_os_busbusy_wake(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
return ret;
}
static int dhdpcie_pm_prepare(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
if (!pch || !pch->bus) {
return 0;
}
bus = pch->bus;
bus->chk_pm = TRUE;
return 0;
}
static int dhdpcie_pm_resume(struct device *dev)
{
int ret = 0;
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
unsigned long flags;
if (pch) {
bus = pch->bus;
}
if (!bus) {
return ret;
}
DHD_GENERAL_LOCK(bus->dhd, flags);
DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
if (bus->dhd->up)
ret = dhdpcie_set_suspend_resume(bus, FALSE);
DHD_GENERAL_LOCK(bus->dhd, flags);
DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
dhd_os_busbusy_wake(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
return ret;
}
static void dhdpcie_pm_complete(struct device *dev)
{
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
#if defined(CUSTOMER_HW4_DEBUG)
uint32 pm_dur = 0;
#endif /* CUSTOMER_HW4_DEBUG */
if (!pch || !pch->bus) {
return;
}
bus = pch->bus;
#ifdef WL_TWT
dhd_config_twt_event_mask_in_suspend(bus->dhd, FALSE);
dhd_send_twt_info_suspend(bus->dhd, FALSE);
#endif /* WL_TWT */
bus->chk_pm = FALSE;
#if defined(CUSTOMER_HW4_DEBUG)
dhd_iovar(bus->dhd, 0, "pm_dur", NULL, 0, (char *)&pm_dur, sizeof(pm_dur), FALSE);
DHD_ERROR(("%s: PM duration(%d)\n", __FUNCTION__, pm_dur));
#endif /* CUSTOMER_HW4_DEBUG */
return;
}
#else
static int dhdpcie_pci_suspend(struct device *dev)
{
int ret = 0;
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
unsigned long flags;
int timeleft = 0;
uint bitmask = 0xFFFFFFFF;
if (pch) {
bus = pch->bus;
}
if (!bus) {
return ret;
}
#if defined(DEVICE_TX_STUCK_DETECT) && defined(ASSOC_CHECK_SR)
dhd_assoc_check_sr(bus->dhd, TRUE);
#endif /* DEVICE_TX_STUCK_DETECT && ASSOC_CHECK_SR */
DHD_GENERAL_LOCK(bus->dhd, flags);
if (!DHD_BUS_BUSY_CHECK_IDLE(bus->dhd)) {
DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
DHD_ERROR(("%s: wait to clear dhd_bus_busy_state: 0x%x\n",
__FUNCTION__, bus->dhd->dhd_bus_busy_state));
timeleft = dhd_os_busbusy_wait_bitmask(bus->dhd,
&bus->dhd->dhd_bus_busy_state, bitmask,
DHD_BUS_BUSY_SUSPEND_IN_PROGRESS);
if ((timeleft == 0) || (timeleft == 1)) {
DHD_ERROR(("%s: Timed out dhd_bus_busy_state=0x%x\n",
__FUNCTION__, bus->dhd->dhd_bus_busy_state));
return -EBUSY;
}
} else {
DHD_BUS_BUSY_SET_SUSPEND_IN_PROGRESS(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
}
#ifdef DHD_CFG80211_SUSPEND_RESUME
dhd_cfg80211_suspend(bus->dhd);
#endif /* DHD_CFG80211_SUSPEND_RESUME */
if (!bus->dhd->dongle_reset)
ret = dhdpcie_set_suspend_resume(bus, TRUE);
DHD_GENERAL_LOCK(bus->dhd, flags);
DHD_BUS_BUSY_CLEAR_SUSPEND_IN_PROGRESS(bus->dhd);
dhd_os_busbusy_wake(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
return ret;
}
static int dhdpcie_pci_resume_early(struct device *dev)
{
int ret = 0;
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
uint32 pmcsr;
if (pch) {
bus = pch->bus;
}
if (!bus) {
return ret;
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 9))
/* On fc30 (linux ver 5.0.9),
* PMEStat of PMCSR(cfg reg) is cleared before this callback by kernel.
* So, we use SwPme of FunctionControl(enum reg) instead of PMEStat without kernel change.
*/
if (bus->sih->buscorerev >= 64) {
uint32 ftnctrl;
volatile void *regsva = (volatile void *)bus->regs;
ftnctrl = pcie_corereg(bus->osh, regsva,
OFFSETOF(sbpcieregs_t, ftn_ctrl.control), 0, 0);
pmcsr = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_PMCSR, sizeof(pmcsr));
DHD_ERROR(("%s(): pmcsr is 0x%x, ftnctrl is 0x%8x \r\n",
__FUNCTION__, pmcsr, ftnctrl));
if (ftnctrl & PCIE_FTN_SWPME_MASK) {
DHD_ERROR(("%s(): Wakeup due to WLAN \r\n", __FUNCTION__));
}
} else
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 9)) */
{
pmcsr = OSL_PCI_READ_CONFIG(bus->osh, PCIE_CFG_PMCSR, sizeof(pmcsr));
DHD_ERROR(("%s(): pmcsr is 0x%x \r\n", __FUNCTION__, pmcsr));
if (pmcsr & PCIE_PMCSR_PMESTAT) {
DHD_ERROR(("%s(): Wakeup due to WLAN \r\n", __FUNCTION__));
}
}
/*
* TODO: Add code to take adavantage of what is read from pmcsr
*/
return ret;
}
static int dhdpcie_pci_resume(struct device *dev)
{
int ret = 0;
struct pci_dev *pdev = to_pci_dev(dev);
dhdpcie_info_t *pch = pci_get_drvdata(pdev);
dhd_bus_t *bus = NULL;
unsigned long flags;
if (pch) {
bus = pch->bus;
}
if (!bus) {
return ret;
}
DHD_GENERAL_LOCK(bus->dhd, flags);
DHD_BUS_BUSY_SET_RESUME_IN_PROGRESS(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
if (!bus->dhd->dongle_reset)
ret = dhdpcie_set_suspend_resume(bus, FALSE);
DHD_GENERAL_LOCK(bus->dhd, flags);
DHD_BUS_BUSY_CLEAR_RESUME_IN_PROGRESS(bus->dhd);
dhd_os_busbusy_wake(bus->dhd);
DHD_GENERAL_UNLOCK(bus->dhd, flags);
#if defined(DEVICE_TX_STUCK_DETECT) && defined(ASSOC_CHECK_SR)
dhd_assoc_check_sr(bus->dhd, FALSE);
#endif /* DEVICE_TX_STUCK_DETECT && ASSOC_CHECK_SR */
#ifdef WL_TWT
dhd_config_twt_event_mask_in_suspend(bus->dhd, FALSE);
dhd_send_twt_info_suspend(bus->dhd, FALSE);
#endif /* WL_TWT */
#ifdef DHD_CFG80211_SUSPEND_RESUME
dhd_cfg80211_resume(bus->dhd);
#endif /* DHD_CFG80211_SUSPEND_RESUME */
return ret;
}
#endif /* DHD_PCIE_RUNTIMEPM */
#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state, bool byint)
#else
static int dhdpcie_set_suspend_resume(dhd_bus_t *bus, bool state)
#endif /* DHD_PCIE_NATIVE_RUNTIMEPM */
{
int ret = 0;
ASSERT(bus && !bus->dhd->dongle_reset);
#ifdef DHD_PCIE_RUNTIMEPM
/* if wakelock is held during suspend, return failed */
if (state == TRUE && dhd_os_check_wakelock_all(bus->dhd)) {
return -EBUSY;
}
mutex_lock(&bus->pm_lock);
#endif /* DHD_PCIE_RUNTIMEPM */
/* When firmware is not loaded do the PCI bus */
/* suspend/resume only */
if (bus->dhd->busstate == DHD_BUS_DOWN) {
ret = dhdpcie_pci_suspend_resume(bus, state);
#ifdef DHD_PCIE_RUNTIMEPM
mutex_unlock(&bus->pm_lock);
#endif /* DHD_PCIE_RUNTIMEPM */
return ret;
}
#ifdef DHD_PCIE_NATIVE_RUNTIMEPM
ret = dhdpcie_bus_suspend(bus, state, byint);