Add HACK@DAC 2021

.gitignore

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+.DS_Store

build/make_run_user_with_pk.sh

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+user_prog=$1
+echo running user program: $1.c
+cd ../software
+export PATH=${PITON_ROOT}/../tools/riscv_gcc/bin:$PATH
+riscv64-unknown-elf-gcc -fno-builtin-printf ariane_api.c syscalls.c $1.c -o user_program.elf
+cd ../pk
+./make_embedded.bash
+cp build/pk ../build/diag.exe
+cd ../build
+rv64_img
+cd $PITON_ROOT/build

make_run_user_with_pk.sh

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+user_prog=$1
+echo running user program: $1.c
+cd ../software
+export PATH=${PITON_ROOT}/../tools/riscv_gcc/bin:$PATH
+riscv64-unknown-elf-gcc -fno-builtin-printf ariane_api.c syscalls.c $1.c -o user_program.elf
+cd ../pk
+./make_embedded.bash
+cp build/pk ../build/diag.exe
+cd ../build
+rv64_img
+cd $PITON_ROOT/build

piton/ariane_build_tools.sh

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+#!/bin/bash
+# Copyright 2018 ETH Zurich and University of Bologna.
+# Copyright and related rights are licensed under the Solderpad Hardware
+# License, Version 0.51 (the "License"); you may not use this file except in
+# compliance with the License.  You may obtain a copy of the License at
+# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
+# Date: 26.11.2018
+# Description: This script builds the RISCV toolchain, benchmarks, assembly tests
+# the RISCV FESVR and the RISCV Torture framework for OpenPiton+Ariane configurations.
+# Please source the ariane_setup.sh first.
+#
+#
+# Make sure you have the following packages installed:
+#
+# sudo apt install \
+#          gcc-7 \
+#          g++-7 \
+#          gperf \
+#          autoconf \
+#          automake \
+#          autotools-dev \
+#          libmpc-dev \
+#          libmpfr-dev \
+#          libgmp-dev \
+#          gawk \
+#          build-essential \
+#          bison \
+#          flex \
+#          texinfo \
+#          python-pexpect \
+#          libusb-1.0-0-dev \
+#          default-jdk \
+#          zlib1g-dev \
+#          valgrind \
+#          csh
+
+
+echo
+echo "----------------------------------------------------------------------"
+echo "building RISCV toolchain and tests (if not existing)"
+echo "----------------------------------------------------------------------"
+echo
+
+if [[ "${RISCV}" == "" ]]
+then
+    echo "Please source ariane_setup.sh first, while being in the root folder."
+else
+
+  #git submodule update --init --recursive piton/design/chip/tile/ariane
+
+  ## parallel compilation
+  #export NUM_JOBS=4
+
+  #cd piton/design/chip/tile/ariane/
+
+  ## not all tools are required at the moment
+  #ci/make-tmp.sh
+  #ci/build-riscv-gcc.sh
+  #ci/install-fesvr.sh
+  ## ci/build-riscv-tests.sh
+  ## ci/install-dtc.sh
+  #ci/install-spike.sh
+  ## ci/get-torture.sh
+  #ci/install-verilator.sh
+
+  ## build the RISCV tests if necessary
+  #VERSION="7cc76ea83b4f827596158c8ba0763e93da65de8f"
+  #cd tmp
+
+  #[ -d riscv-tests ] || git clone https://github.com/riscv/riscv-tests.git
+  #cd riscv-tests
+  #git checkout $VERSION
+  #git submodule update --init --recursive
+  #autoconf
+  #mkdir -p build
+
+  ## link in adapted syscalls.c such that the benchmarks can be used in the OpenPiton TB
+  #cd benchmarks/common/
+  #rm syscalls.c util.h
+  #ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/syscalls.c
+  #ln -s ${PITON_ROOT}/piton/verif/diag/assembly/include/riscv/ariane/util.h
+  #cd -
+
+  #cd build
+  #../configure --prefix=$ROOT/tmp/riscv-tests/build
+
+  #make clean
+  #make isa        -j${NUM_JOBS} > /dev/null
+  #make benchmarks -j${NUM_JOBS} > /dev/null
+  #make install
+  cd ${PITON_ROOT}
+
+  echo
+  echo "----------------------------------------------------------------------"
+  echo "build complete"
+  echo "----------------------------------------------------------------------"
+  echo
+
+fi

piton/ariane_setup.sh

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+#!/bin/bash
+# Copyright 2018 ETH Zurich and University of Bologna.
+# Copyright and related rights are licensed under the Solderpad Hardware
+# License, Version 0.51 (the "License"); you may not use this file except in
+# compliance with the License.  You may obtain a copy of the License at
+# http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+# or agreed to in writing, software, hardware and materials distributed under
+# this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+# CONDITIONS OF ANY KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations under the License.
+#
+# Author: Michael Schaffner <schaffner@iis.ee.ethz.ch>, ETH Zurich
+# Date: 26.11.2018
+# Description: This script sets up some environment variables for the
+# OpenPiton+Ariane simulation and build flow. Important: use a bash shell
+# for this, and source it while being in the root folder of OpenPiton.
+#
+# Make sure you have the following packages installed:
+#
+# sudo apt install \
+#          gcc-7 \
+#          g++-7 \
+#          gperf \
+#          autoconf \
+#          automake \
+#          autotools-dev \
+#          libmpc-dev \
+#          libmpfr-dev \
+#          libgmp-dev \
+#          gawk \
+#          build-essential \
+#          bison \
+#          flex \
+#          texinfo \
+#          python-pexpect \
+#          libusb-1.0-0-dev \
+#          default-jdk \
+#          zlib1g-dev \
+#          valgrind \
+#          csh \
+#          device-tree-compiler
+
+
+echo
+echo "----------------------------------------------------------------------"
+echo "openpiton/ariane path setup"
+echo "----------------------------------------------------------------------"
+echo
+
+echo "make sure that you source this script in a bash shell in the root folder of hackdac21_phase2"
+
+if [ "$0" !=  "bash" ] && [ "$0" != "-bash" ]
+then
+  echo "not in bash ($0), aborting"
+  #return
+
+fi
+
+SCRIPTNAME=ariane_setup.sh
+
+TEST=`pwd`/piton/
+if [[ $(readlink -e "${TEST}/${SCRIPTNAME}") == "" ]]
+then
+  echo "aborting"
+  return
+fi
+
+################################
+# PITON setup
+################################
+
+# set root directory
+export PITON_ROOT=`pwd`
+export ARIANE_ROOT=${PITON_ROOT}/piton/design/chip/tile/ariane/
+
+## GCC and RISCV GCC setup
+export CXX=g++ CC=gcc
+# customize this to a fast local disk
+export RISCV=/scratch/`whoami`/riscv_install
+export VERILATOR_ROOT=$ARIANE_ROOT/tmp/verilator-4.014/
+
+# setup paths
+export PATH=$RISCV/bin:$VERILATOR_ROOT/bin:$PATH
+export LIBRARY_PATH=$RISCV/lib
+export LD_LIBRARY_PATH=$RISCV/lib
+export C_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
+export CPLUS_INCLUDE_PATH=$RISCV/include:$VERILATOR_ROOT/include
+
+# source OpenPiton setup script
+# note: customize this script to reflect your tool setup
+source ./piton/piton_settings.bash
+
+if [[ $(readlink -e "${RISCV}/bin/spike") == "" ]]
+then
+    echo
+    echo "----------------------------------------------------------------------"
+    echo "setup complete."
+    echo "----------------------------------------------------------------------"
+    echo
+else
+    echo
+    echo "----------------------------------------------------------------------"
+    echo "setup complete."
+    echo "----------------------------------------------------------------------"
+    echo
+fi

piton/design/chip/chip_bridge/README

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+current frequency settings:
+Chip:
+Interconnect: 1000Mhz
+FPGA: 200Mhz
+
+TODO: clean variable names

piton/design/chip/chip_bridge/rtl/Flist.chip_bridge

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+// ========== Copyright Header Begin ============================================
+// Copyright (c) 2015 Princeton University
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//     * Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     * Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in the
+//       documentation and/or other materials provided with the distribution.
+//     * Neither the name of Princeton University nor the
+//       names of its contributors may be used to endorse or promote products
+//       derived from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY
+// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ========== Copyright Header End ============================================
+
+sync_fifo.v
+chip_bridge_rcv_32.v
+chip_bridge_send_32.v
+chip_net_chooser_32.v
+chip_bridge.v

piton/design/chip/chip_bridge/rtl/chip_bridge.core

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+CAPI=2:
+name: openpiton::chip_bridge:0.1
+description: chip_bridge testbench
+
+filesets:
+    rtl:
+        files:
+            - sync_fifo.v
+            - chip_bridge_rcv_32.v
+            - chip_bridge_send_32.v
+            - chip_net_chooser_32.v
+            - chip_bridge.v
+        depend:
+            - openpiton::piton_include
+            - openpiton::piton_common
+        file_type: verilogSource-2001
+
+targets:
+    default:
+        filesets: [rtl]
+    pickle:
+        default_tool: icarus
+        filesets: [rtl]
+        toplevel: [chip_bridge]
+        tools:
+            icarus:
+                iverilog_options: [-g 2001 -E]
+    verify:
+        default_tool: icarus
+        filesets: [rtl]
+        toplevel: [chip_bridge]
+        tools:
+            icarus:
+                iverilog_options: [-g 2001]